Synopsys-lithography-verification-in-Proteus-LRC-handles-EUV-double-patterning

March 1, 2011 — Synopsys, Inc. (Nasdaq: SNPS), software and IP provider for semiconductor design, verification and manufacturing, introduced Proteus LRC for lithography verification at SPIE Advanced Lithography, taking place through March 3 in San Jose, CA. Proteus LRC provides comprehensive, process-window-aware checking features to identify locations in a design that are sensitive to process variations, enabling corrective actions prior to committing a semiconductor design to manufacture. Proteus LRC is integrated into the Proteus Mask Synthesis flow.

Proteus LRC is targeted for use by optical proximity correction (OPC) and mask data preparation groups at semiconductor manufacturers at the 28nm node and below. Along with OPC, it offers rigorous first-principle models from embedded Sentaurus Lithography technology. It is imperative for lithography rule check (LRC) tools to accurately predict and verify the critical dimension (CD) variation through the process window for adequate process margins. The Sentaurus Lithography technology allows access to first-principle models for resist profiles and topography effects when identifying at-risk hotspots and determining the appropriate course of action.

At SPIE Advanced Lithography in San Jose, George Bailey, director, technical marketing at Synopsys, describes the data flow process in a podcast interview with Debra Vogler, senior technical editor. View the data and listen to the Synopsys interview here. 

Micron Technology uses Proteus LRC, citing robust checking algorithms and predictable models. “At Micron, it is imperative not to miss any hotspots that would have a negative impact on yield,” said Anthony Krauth, R&D advanced mask development manager at Micron Technology Inc.

New manufacturing techniques like extreme ultraviolet (EUV) lithography and double-patterning technology (DPT) are handled by DPT-specific checking functionality and Proteus Pipeline Technology. DPT-specific checking provides error detection for each exposure and mask misalignment condition with a consolidated results viewing environment. Synopsys’ Proteus Pipeline Technology, introduced at SPIE Advanced Lithography 2008, enables Proteus LRC to efficiently handle the full-chip layout requirements of EUV.

Proteus LRC has been fully integrated in the Proteus Mask Synthesis flow with near-linear scalability to hundreds of standard x86 processor cores. “We integrated Proteus LRC into the Proteus Mask Synthesis flow to allow semiconductor manufacturers to run the entire OPC flow efficiently on standard hardware resources,” said Howard Ko, senior vice president and general manager of the Silicon Engineering Group at Synopsys. “We also embedded Sentaurus Lithography technology in Proteus LRC to provide OPC engineers with the ability to analyze critical hotspots with the highest level of accuracy.”

Visit Synopsys at SPIE Advanced Lithography’s exhibition, through March 2, at Booth 418.

Synopsys Inc. (Nasdaq:SNPS) provides electronic design automation (EDA) software, intellectual property (IP) and services used in semiconductor design, verification and manufacturing. Visit Synopsys online at http://www.synopsys.com/.

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