by Michael A. Fury, Techcet Group
April 27, 2011 – Moscone Center West is a cavernous facility for a meeting of this nature, but the size of each conference room is required for most of the sessions I’ve seen. Wireless Internet access is available in the lobby of the two meeting floors, but most decidedly not inside any of the meeting rooms. I find this to be a great courtesy to the speakers, as the attendees are paying attention rather than checking email as so often happens at other meetings.
The other consequence of having conference rooms with temporary walls (these are otherwise vast exhibition floors, after all) is that there are no wall sockets for recharging laptops. The audio-visual equipment in each meeting room depends on miles of orange extension cords. The easiest way to find a wall plug is to look for the cluster of folks sitting on the floor along the wall in the halls and lobby for no other apparent reason. The eight-hour bra was so much easier to achieve than the eight-hour battery…
(Additional presentation details can be found online on the MRS Spring 2011 abstracts page. The underscored codes at the beginning of papers reviewed below refer to the symposium, session, and paper number.)
Future CMOS, III-V, memory
Jesus del Alamo of MIT (P1.1) reviewed the challenges of CMOS below 22nm, proposing that III-V CMOS provides a path through this age of power-constrained scaling. Maintaining a constant power demand requires reducing the operating voltage. He has built an InAs HEMT FET with the highest fT of any material to date, 681 GHz, and ION that is 2× the benchmark Si devices at 0.5VDD. This is partly attributed to an electron injection velocity that is twice that of silicon. Perhaps the most significant challenge to migrating these devices onto silicon substrates is fabricating Ge PMOS and InGaAs/InP NMOS side-by-side. Future 10nm devices will need to incorporate a quantum well, a raised source/drain and a self-aligned gate based on the best learning to date. A planar FET may not be able to meet the electrostatics requirements, but a 3D structure offers hope.
Iain Thayne of U. Glasgow (P1.5) gazed into the foggy future of III-V MOSFETs at 15nm scaling and beyond. His horizon extends to 2024, with a target gate pitch of 15nm and channel length of 7nm. Experimental data seems to suggest a move from GaAs/Ga2O3 toward In0.53Ga0.47As/Ga2O3 with an Al2O3 cap. Device realization with a gate first process was accomplished with In0.3Ga0.7As/ Ga2O3/GdO for process learning, but additional work is needed.
Jaesoo Ahn of Stanford (P1.7) explored the use of TiO2/Al2O3 bilayer dielectrics as the gate oxide for In0.53Ga0.47As MOSFETs. Removal of the As surface cap prior to gate dielectric deposition creates an atomically abrupt interface. Crystallization of the TiO2 in the bilayer during forming gas anneal generates high-k rutile domains, believed to be responsible for an increase in capacitance that does not occur with an Al2O3 monolayer. The TiO2 bilayer also reduces the leakage current.
Bhaswar Chakrabarti of the U. Texas/Dallas (Q1.3) talked about SiO2/HfO2 stacked films as tunnel-barrier engineered (TBE) structures for flash memory. Such layers should provide better program current and retention than a single SiO2 layer, according to simulations. Tunneling current was measured in simple MOS capacitor stacks. Thick (16nm) HfO2 layers are not suitable for barrier engineering; the temperature dependence indicates trap-assisted tunneling. Traps are still evident in a 3nm HfO2 layer, and are not removed by annealing; this is believed due to growth of an interfacial oxide. The simulation hypothesis was not supported.
Willi Volksen of IBM Almaden Research (O1.3) re-opened the CVD vs. spin-on low-k dielectric debate with the introduction of a base-catalyzed sol-gel material with a k value of 2.4 that is reportedly extendable to k=1.8. Emphasis is on molecular reinforcement of the pore system with the objective of reducing plasma etch damage. The work is a collaboration with JSR.
Continuing on the resurgence of spin-on low-k, UT/D’s Suresh Regonda (O1.5) presented on a polysilazane material designed for STI trench fill <32nm. Target trench specs were AR>20 with a top width <25nm (<10nm at bottom). Preliminary results show 20MV/cm @ 400°C and 12MV/cm @ 800°C. Dongjin supplied the SOD material.
Anthony Grunenwald of the European Membrane Institute in Montpellier, France (O1.4), described the design of hydrophobic ultralow-k (ULK) materials with isolated mesopores. Copolymer films were calcined at 450°C or treated with UV-thermal at 400°C. The UV-thermal was unsuccessful for complete removal of the porogen. While fundamental learning took place, the materials are not ready for prime-time.
Shoko Ono of Mitsui Chemicals’ R&D center (O2.4) described the quest for a wet process for a stable, ultra-thin pore seal for porous low-k dielectrics. The aqueous system with undisclosed ingredients leaves a conformal 2-3nm continuous layer that is stable to 350°C. Cu diffusion measurement by triangular voltage sweep indicates complete suppression of Cu ion drift to 125°C.
Xin Liu of Arizona State U. (O2.3) talked about a N2/H2 plasma process for simultaneous cleaning of post-CMP low-k and Cu surfaces. The ILD studies was a low carbon 25% porosity material with k of 2.5. Plasma treatment tends to leave a hydrophilic surface that causes k to increase on standing in air; the mechanism was hypothesized but a solution was not. The Cu cleaning seems to be effective with no downside.
John Zhang of STMicroelectronics (O3.1) talked about the challenges in achieving CMP planarity at the contact level posed by the presence of both tensile and compressive nitride films on the working surface. The tensile nitride has a removal rate 30% higher than the compressive nitride. Proper choice of the deposition sequence allows planarization to occur without generating local stress gradients that create defects within the device.
Lucy Nolan of the U. of Alberta (O3.3) talked about fluid flow characteristics in CMP. On the platen, the slurry flow is treated as laminar and steady state, but is modified by the pad groove pattern and depth (pads from Cabot Microelectronics and NexPlanar were used). With deeper grooves, slurry velocity and acceleration across the pad is impeded, resulting in different slurry delivery dynamics at the wafer interface. The hypothesis of slurry starving at the outer radius of the pad was not supported.
Dries Van Gestel of IMEC (A3.1) expounded on the poly-Si PV target efficiency of 14%-15% for the technology’s commercial viability, which is only slightly higher than today’s hypothetical best case of 12.4%. Defect reduction is one stumbling block, which might be best addressed by laser recrystallization. Shifting from p type to n type doping is another is another change proscribed by the hypothetical best case. Early experimental results indicate a reasonable feasibility. Surface texturing, Ag nanoparticle plasmons, and advanced light-trapping designs are other features that are expected to be necessary to achieve 14%.
Joop van Deelen at TNO in Eindhoven (C2.9) put metal grids on top of TCO films to meet the needs of both short and long distance charge transport. His test vehicle was 45Ω/sq ITO on PET with a Cu grid consisting of 8μm to 60μm wide lines with an aspect ratio of 0.45 and total shading of 6% to 13%. A representative PV cell improved from 117 W/m2 to 138 W/m2 output.
Nanowires, graphene, nanotubes
Adele Tamboli at Caltech (EE1.9) showed a technique for wafer-scale growth of Si microwire arrays using SiCl4 CVD with a Cu catalyst. Wires with a length of 50μm could be lifted off with PDMS, resulting in a flexible vertical array adaptable for PV applications. Light scattering showed a uniform array of wires, including an on-sight generation of a nice diffraction pattern using a laser pointer.
Ilia Ivanov at Oak Ridge National Lab (G1.8) is addressing the 4Bm2 annual market for display glass with his studies of transparent conductive coatings using carbon nanotubes (CNT). As manufactured, SWNTs are typically 1/3 metallic and 2/3 semiconducting; the semiconducting CNT reduce transmittance without contributing to conduction. Whereas carbon black requires up to 10wt% for conductivity, metallic CNT requires <1wt%. Frequency dependent impedance spectroscopy can generate macroscopic data that separates bundle resistance from junction resistance, providing a conduction percolation analysis of the CNT network. The data suggests that touch panel conductivity requirements can be met with an adequate volume production method for separated metallic CNT.
Phaedon Avouris of IBM Watson (P2.4) expounded on the challenges of using graphene for RF transistors and ultrafast photo detectors. Metal-graphene contacts are as resistive as the channel resistance itself. Wafer-scale graphene fabrication from Si thermal desorption of SiC yields micron-sized terraces with direction-sensitive resistivity ranging from 1kΩ-40kΩ within 5μm of each other, and so must be used with caution. Experimental device channels are now fabricated only on a single terrace. A device with 240nm channel length gave fT of 230GHz. CVD graphene grown on Cu is said to be more reliable as it can be grown a single crystal tens of μm across with low defects, and it is mechanically transferrable to other surfaces. The CVD graphene yielded a device with fT 155GHz at a 40nm channel length. A unipolar frequency mixer was chosen to demonstrate that graphene can be integrated into a complete IC processing environment. A photo detector with interdigitated Pd and Ti electrodes was fabricated and achieved reliable 10Gbit/sec data transmission.
Byung Jin Cho at KAIST (QQ4.1) described the use of graphene in ReRAM. The switching mechanism is dominated by oxygen diffusion, and not electrode metal filament formation. Memory cycling endurance is limited by metal diffusion. The electrode surface must be below a RMS roughness of 4nm in order for devices to reliable exhibit switching without breakdown..
Antonio Facchetti of Northwestern U. and Polyera Corp. (T2.2) reviewed synthesis and fabrication strategies for organic, inorganic and hybrid materials for printed transistors. This served as prelude to his introduction of a new high-mobility electron-transporting organic semiconductor family based on the naphthalene diimide core. In amino-functionalized SAM dielectrics, the large positive calculated dipole moment contradicts the device behavior indicative of a negative dipole. The proposed explanation is that the amino transfers a charge to the silanol end, creating a zwitterion that behaves as a negative dipole. High mobility purity dense metal oxide films have been formed by in situ self-combustion chemistry.
Sanghyuk Kim of KAIST (T2.9) showed the results of nanoscale patterning using a two-step transfer printing process. A silver nanoparticle ink was coated on a donor substrate, lifted off with a patterned PDMS stamp and transferred to a target substrate. Following removal of the soft transfer PDMS, the Ag was annealed at 140°C to remove the excess solvent and sinter the nanoparticles. Transfer printing onto non-planar target substrates with 10μm step heights was demonstrated with good stamp pattern integrity.
Alasdair Campbell of Imperial College London (T2.10) described gravure printing for high-performance polymer LED devices for large-area displays and lighting. Gravure in conventional applications can print at 60m2/sec, making its throughput quite attractive. Polymer solvent systems must be carefully adapted for compatibility with the gravure process for film formation without a host of defects including wrinkling, delamination, surface roughness, and non-uniformity. A PEDOT:PSS LEP PLED gravure device was achieved with electrical parameters equivalent to a conventional spin coated device. An inverted hybrid PLED with a Cs2CO3 layer was 4×-5× better with gravure printing than conventional devices in terms of both current efficiency and power efficiency. It is thought that gravure produces a more interconnected amorphous morphology that improves electron injection.
Michael A. Fury, Ph.D, is senior technology analyst at Techcet Group, LLC, P.O. Box 29, Del Mar, CA 92014; e-mail email@example.com.