by John Behnke, VP of worldwide sales and marketing, Intermolecular Inc.
May 19, 2011 – The SEMI/IEEE Advanced Semiconductor Manufacturing Conference wrapped up today (May 18) leaving lots of good information and food for thought in the minds of attendees.
Tuesday evening featured a drive-by tour of GlobalFoundries’ Fab 8, at its beautiful sylvan site in the middle of the Luther Forest Technology Campus. It’s a gorgeous building in an amazing natural setting, with lots of room for expansion. There was some disappointment, though, that we weren’t able to go inside where all the really interesting stuff is going on!
After a turn past some of the historic sites of Saratoga Springs, ASMC attendees were hosted at the historic Canfield Casino by community leaders including Mayor Scott Johnson. It was a great event with lots of good networking; it’s always fun for us techno-nerds to get the red carpet treatment. I’ll give a big shout-out to the whole community of Saratoga Springs — literally every person we came in contact with was hospitable, kind, and friendly, and it’s been a pleasure to spend time here.
Wednesday kicked off with an EUV lithography tutorial from Obert Wood, principal member of technical staff in GlobalFoundries’ strategic lithography technology department. (Wood, who spent 34 years at Bell Labs, is something of a living legend in EUV, and he did not disappoint — his tutorial was informative, honest, and richly detailed, and attended by pretty much everyone at the conference.) EUV’s throughput is still way below where it needs to be, he acknowledged: Current machines are running on the order of one wafer per hour, but the technology is moving forward. Wood predicted that double-patterned 193nm lithography would still be the mainstay at the 14nm node, with EUV coming fully on line at 10nm.
Source output is still an issue. Wood discussed the competing options from Cymer and Xtreme, and said Cymer’s laser-based approach might have more merit for ultimate power needs. In response to an audience question, he said that EUV exposure tools require a whopping 350kW of input power, due to inefficiencies in both the source itself and the EUV optics. Less than 2% of that power actually reaches the wafer.
Other primary hurdles are reticle defectivity (although Intel has produced one functioning if not defect-free logic reticle, Wood noted), and line-edge roughness (LER) in resists. As a former etch guy, I was glad to hear him discuss the collaboration that’s going on between lithography and etch teams to address LER — it’s much better to work together than to argue about whose problem it is.
|Day 1: Rain doesn’t damper the spirit|
|Day 2: Approaching device scaling, manufacturing challenges with partnerships|
|Day 3: EUV, image sensors, and a capital perspective|
One last EUV tidbit: it looks like the reticle defect issue will be much more of a problem for logic, as memory makers can continue their tradition of adding redundant capacity and cutting it in at the test stage as needed. This, coupled with the reticle limitations associated with logic, leads me to believe that EUV will make its mark first in memory.
Another interesting talk given by Ray Fontaine of Chipworks covered the booming CMOS image sensor market. Sensors have gone from being trailing-edge devices to demanding high-end products, made on 300mm wafers using 40nm processes and exotic materials such as hafnium oxide and tantalum oxide. Some 1.7 billion image sensors were sold in 2010, he said, with continuing pressure for smaller form factors, faster response, and better resolution and image processing. There’s a tremendous amount of innovation going on in this area — Fontaine noted that while sensors traditionally required four transistors per pixel, newer designs have made substantial reductions, with Sony now using transistor sharing to bring the total to just 1.375 per pixel.
Youssef Baltagi of STMicroelectronics presented some very promising results from ST’s use of embedded memory failure analysis for production yield enhancement. With more and more devices having embedded memory, it makes a convenient indicator that can help localize, identify, and classify failure modes. The use of built-in self-test (BIST) makes it even easier. This is a concept that’s been used for some time, but the ST results show that it’s become a real-world means of extracting process data and improving yield learning.
The final talk was one of my favorites of the week: Peter Wright, director of research at Tradition Equities, speaking on "A capital markets view on manufacturing." Investment can often be a dry subject, but Wright was a strong and engaging speaker on the complex subject of analyzing and evaluating markets. He cited three pillars of evaluation: fundamentals, valuation, and sentiment. Wright was bullish on the semi market over the coming decade, as semiconductor-sector companies have traditionally delivered better growth than the market as a whole, and valuations, he said, are currently at record low multiples.
On the sentiment side, Wright made the interesting point that the semiconductor sector may have underperformed over the past decade as a result of chip companies putting more focus on efficiency instead of innovation. He predicted that this would change in the years ahead, with revolutionary changes coming to market, including big advances in energy, environmental interactions, and what he called "new age" electronics.
That’s a good and encouraging note to end the conference on, and SEMI and the IEEE deserve credit for executing so well on the difficult task of making a broad-based event like ASMC so relevant and useful to attendees from different parts of the industry.
Thanks to everyone for the good conversations this week, and to those who gave us positive feedback on these postings. It’s been a pleasure, and we hope to do it again at future conferences.