Benchmark “mid-end” tools and materials for 3DIC and wafer-level packaging (WLP)

May 13, 2011 – Yole Développement released "Equipment & Materials for 3DIC and Wafer-Level-Packaging," a database and complete report analyzing in detail the equipment and materials tool-box for wafer-level packaging (WLP).

Wafer-level packaging is the name given to an array of technologies: historically flip-chip wafer bumping with electroplated gold and solder bumps and leading-edge copper pillars. Form factors include fan-in WLCSP packages, 3D WLP, FO WLP packages, 2.5D glass/silicon interposers and 3DIC integration with TSV interconnects.

A real infrastructure has emerged into what is now being called the mid-end of the semiconductor manufacturing environment (the overlapping area that is served by IDM/CMOS foundry backend of line [BEOL] processes and the OSAT/wafer bumping house back-end wafer bumping assembly). There’s a significant difference in how manufacturing is generally performed in the front-end versus the back-end.

Yole’s analysts gathered all the information necessary to benchmark and compare all the different alternatives offered by the present equipment and material tool-box for wafer-level-packaging. All main scenarios are analyzed, including flip-chip wafer bumping trends, Fan-in WLCSP, 3D WLP, FOWLP, 2.5D silicon interposers, 3DIC Via Middle & Via Last processes. Yole includes a 2010-2016 wafer forecast for each "flavor."

The backend has greater cost sensitivity with adaptability for scaling with time, as ICs shrink and pin counts increase. Frontend technologies are more expensive initially, but offer higher repeatability, yield, and throughput. Frontend technologies allow chip makers to scale down the technology to smaller pitch dimension while maintaining cost pressure.

Future trends for PANEL scale packaging (embedded die in PCB, FOWLP 2nd generation and polysilicon or glass sheet interposers based on LCD/PCB/Solar infrastructures) are also analyzed.

WLP has emerged as the fastest growing semiconductor packaging technology with more than 27% CAGR in unit shipments over the next 5 years. The wafer-level-packaging market shows the greatest potential for significant  future growth in the semiconductor industry. Yole expects the equipment and material market for wafer-level packaging to grow significantly in total revenue over the next five years with a CAGR over 60%. The growth will be mainly driven by the expansion of flip-chip, WLCSP and FOWLP technologies into the wireless mobile industry along with the emergence of 3DIC technology into 3D TSV stacked memories, wide I/O interfaces in logic and memory ICs as well as in CMOS image sensors, MEMS and other heterogeneous 3D stacking applications.

The analysis quantifies the WLP equipment market evolution for wafer bonders, die pick & place bonders, C2W bonders, DRIE etching & drilling tools, CVD, PVD, plating, exposure & lithography, spray coating, temporary bonding & de-bonding, grinding-thinning-CMP, wafer-molding, inspection & metrology, and test tools.

On the material side, it covers photoresist & coatings, adhesive tapes, pre-applied & wafer-level underfills, molding compounds, thermal interface materials (TIM), plating/etching/cleaning chemistries, slurries for CMP, temporary bonding materials, gas & precursors, sputtering targets, silicon & glass wafer carriers, cap, 2.5D interposer and TSV substrates.

Wafer-level packaging tool providers are consolidating, Yole says, pointing to Applied Materials’ acquisition of Semitool, which enabled AMAT to expand and sustain in this back-end/WLP direction.

Along with this new research report, Yole will be delivering a 350+ players excel database screening and profiling the detailed activity of small, medium, and giant equipment & material suppliers coming either from Front-end, Back-end assembly, PCB, LCD or Solar industries and providing actual solutions for the 3DIC & wafer-level-packaging tool-box.

WLP equipment & material market forecasts are given in unit, volume and revenues 2010-2016, with estimated sales opportunities in the global mid-end 3DIC & wafer-level-packaging area.

Report authors:
Phil Garrou recently joined Yole Développement forces as senior technical advisor in the fields of advanced packaging. He blogs for ElectroIQ.com at Insights from the Leading Edge.

Jerome Baron is leading the advanced packaging market research at Yole Developpement.

Access the report at http://www.i-micronews.com/reports/Equipment-Materials-3DIC-Wafer-Level-Packaging/204/

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