Non-planar device scaling: SEMATECH talks TSV, SoC, SiP

May 18, 2011 — For the first time, the semiconductor industry is moving to 3D device structures, such as through silicon vias. This is significantly different than moving to thinner devices, says Raj Jammy, SEMATECH, at The ConFab 2011. He speaks with senior technical editor Debra Vogler.

Conformality of the gate dielectric, conformality of the contacts, and design all come into play. Semiconductor makers must still create robust and high-yield devices to be sucessful.

The biggest challenges for high-volume manufacturing of through silicon vias (TSV), Jammy says, are all through the process flow. Bonding and de-bonding is one major example, with poor throughput. Materials stresses, especially on thinned dies, are another.

SoC technologies are on the verge of some significant changes, Jammy predicts. For example, an entire smartphone could be fit onto one SoC. With system in package (SiP), additional functionality will be integrated, even MEMS devices.

Jammy also reviews SEMATECH’s roadmaps for logic and memory.

Read a summary of Jammy’s ConFab 2011 presentation on new device architectures.

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