Tighter chip densities tease out litho, metrology weaknesses, says Intel

May 18, 2011 — Janice Golda, Intel, co-led a session at The ConFab 2011 on continued device scaling. EUV infrastructure will be a major topic, as well as transistor challenges. Device and materials options abound, but so does the risk.

Golda speaks with senior technical editor Debra Vogler.

The scaling roadmap will continue along Moore’s Law, scaling down to double density each generation. For 22nm and trigate, litho challenges are similar to what you’d have in other architectures, says Golda. There are more challenges in metrology and inspection, where defects easily hide in complex structures. Golda expects their session at The ConFab to demonstrate the interconnectivity of litho, wafer processing, and metrology challenges, as well as the business side of new technologies.

More from the ConFab:

 

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