New architectures, litho schemes take the stage at SEMICON West by David Lammers, SEMI contributing editor June 24, 2011 - The semiconductor industry is at a crossroads, with new architectures needed to continue scaling both logic and memory devices. In May, Intel surprised many by saying it will switch from a planar to a vertical FinFET transistor at the 22nm node, coming to market in MPUs late this year. What will other companies do? Emerging architectures for logic and memories Tuesday, July 12, 10:30-12:30 Three speakers will describe possible successors to today’s CMOS transistors. Serge Biesemans, VP of process technology at Imec, will give his thoughts on FinFETs, while Ali Khakifirooz, ETSOI lead device engineer at IBM Research, will discuss the advantages of a planar device on an extremely thin silicon-on-insulator substrate. Raj Jammy, VP of materials and emerging technologies at SEMATECH, will describe how germanium and III-V materials can be combined in heterogeneous ICs. In the memory portion of this TechXPOT, SEMATECH researcher David Gilmer will provide a progress report on metal-oxide-based resistive RAMs, an area of intense study worldwide. Two other speakers will describe the challenges of building vertically stacked NAND memory cells, called cell array transistor (CAT) memories. Bart van Schravendijk, CTO at Novellus Systems, and Gill Lee, a senior director at Applied Materials, each will describe the processes required to build vertically integrated memories. Advanced lithography Wednesday, July 13, 10:30-12:30 Major challenges remain for the future of lithography, both in the EUV sources and in the options for extending 193nm immersion. How to generate enough EUV photons is the major challenge for EUV scanners. Michael Lercel, a former IBM lithography research manager, now working as a senior director at Cymer, will discuss the current state of the laser-produced plasma (LPP) EUV source power modules. Mark Corthout, president of Xtreme Technologies, will provide an update on the competing approach to source power: discharge-produced plasma (DPP) modules. Skip Miller, a director at ASML, will detail the EUV scanners now being used for process development and prototyping. And Stefan Wurm, EUV research manager at SEMATECH, will describe the Sematech-led EUVL Mask Infrastructure Partnership. The second hour of the Advanced Lithography TechXPOT will consider methods to extend 193nm scanners, including presentations from Martin McCallum, program manager at Nikon Precision Europe, and Chris Bencher, a member of the technical staff at Applied Materials. David Lam, founder of Lam Research and now the chairman and CEO of Multibeam, will describe how direct-write e-beam lithography can complement today’s scanners for future technology generations.