SEMICON West workshop addresses stress management for 3D ICs using TSVs

July 19, 2011 – Management of mechanical stresses is one of the key enablers for the successful implementation of 3D integrated circuits using through-silicon vias (TSVs). The stress-related impact of the processing done at the various companies in the manufacturing supply chain needs to be characterized and shared, and designers need a DFM-like solution for managing stress.

In conjunction with SEMICON West, SEMATECH and Fraunhofer IZFP hosted "Stress management for 3D ICs using through silicon vias: Product-level reliability workshop" to address product level considerations for dealing with stress-driven reliability mechanisms of the via-middle through-silicon-via (TSV) 3D stacking technologies. On Thursday, July 14, technologists and technology managers from various companies and institutions in the US, Asia, and Europe gathered to examine what is required at the product level to managing stress in 3D interconnects, and to drive consensus and support for these techniques across the industry.

In a series of invited talks, speakers discussed the following:

  • Keynote presenter Mark Nakamoto of Qualcomm shared a high-level perspective of product reliability and new risks associated with the use of new features: TSVs and microbumps, new materials and processes, and new chip package interactions using thinned die and hard microbumps.
  • Eric Beyne of IMEC presented on failure analysis challenges and techniques including X-ray tomography, magnetic current imaging, time domain reflectometry, photon emission microscopy, SAM, lock-in thermography, IR, and SAW based techniques.
  • Ron Huemoeller of Amkor discussed some of the new failure mechanisms that might not be addressed by traditional package qualification tests, and concluded that a paradigm shift in engineering for reliability is needed.
  • TSV intrinsic reliability and reliability qualification challenges was presented by You-Wen Yau of Qualcomm CDMA Technologies.
  • Suresh Ramalingam of Xilinx discussed the current status of reliability testing, stress simulations, and failure mode analysis for his company’s Stacked Silicon Interconnect Technology.

In the afternoon, a working session focused on discussing failure mechanisms, test structures, material characteristics, measurement techniques, and modeling techniques.

On Wednesday, October 12, in conjunction with SEMICON Europa, a sixth workshop, hosted by Fraunhofer IZFP in collaboration with SEMATECH, will focus on reliability-limiting degradation kinetics.

SEMATECH is hosting a 3D Interconnect wiki site to provide a forum to the community to discuss the issues raised in these workshops.

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