September 20, 2011 — D2S announced a mask-wafer double simulation accelerated workstation, TrueMask DS, for R&D exploration, bit-cell design, hot-spot analysis and mask defect categorization at the SPIE Photomask Technology conference (i.e., BACUS, 9/19-9/22/11, Monterey, CA).
Mask shops and wafer fabs can use the new tool for qualifying and optimizing 20nm node and below semiconductor designs. At these nodes, the assist features on the photomasks are smaller than 80nm and can no longer be reliably produced. The purpose of the new simulation tool is to enable the efficient exploration of the various trade-offs including complex optical proximity correction (OPC), inverse lithography technology (ILT), source mask optimization (SMO), and the cost and turnaround time of masks for critical circuits.
"It’s an exploration platform that allows designers to explore shapes that can be efficiently written on mask writers and is also best for wafer yield," said Aki Fujimura, CEO, D2S (and managing company sponsor of the eBeam Initiative). "In 20nm and below nodes, unlike previous nodes, mask shapes, mask write times, and wafer yields are becoming trade-offs against each other." The new platform allows exploration of the trade-offs.
|Figure 1. Sub-80nm discontinuity in semiconductor manufacturing.|
Fujimura explains in the podcast interview below that accuracy inherent in mask writers is impacted at 20nm and below. "For mask writing, which is based on 50keV e-beams, discontinuity occurs below 80nm sizes," he said (Fig. 1). He further notes that above 80nm mask dimensions, one could count on the shot size being faithfully reproduced on the mask surface. Going below 80nm, one is no longer is able to get the same shape nor will the size be reproduced every time, nor will the printed feature be reliable in size, he added. Therefore, "lithography simulation is no longer enough." Also, the lithography simulation methodology the industry has been for over 10 years — known as the bundled model — counts on a mask being accurate enough, which as just explained, is no longer true. By using a separated mask model instead of the typical bundled model, the new workstation modeling includes the mask effects. An independent validation of the mask-wafer double simulation approach is shown in the table.
|Table. Independent validation of mask-wafer double simulation approach. In this example, the D2S MB-MDP of ILT mask shapes is the best choice for better wafer quality (lower PV band) and faster mask write time (lower shot count). Courtesy Globalfoundries, BACUS 2011 paper #8166-110, Gek Soon Chua, et al.|
Conventional mask shapes
|ILT Manhattanized mask shapes||D2S MB-MDP of ILT mask shapes||Ideal OPC data|
|Worst PV band||2.18X||2.15X||1.75X||1.64X|
|Shot count increase||1X||5X||3X||8|
Fujimura also noted that the new platform is important for cost reduction (Fig.2). A typical cycle for doing mask simulation followed by lithography simulation might be hours of work. Because the new system uses a graphics processing unit (GPU) accelerator, the amount of work will be reduced to tens of seconds. Being able to get the feedback on the impact of changing mask shapes in such a short period of time enables substantial time savings on the trade-off evaluation.
|Figure 2. Bending the mask cost curve. SOURCE: IBS Inc.|
Other features of the platform include: 0.1nm resolution mask simulation up to 300 x 300