EUV Symposium: Updates on defects, resists, AIMS, and non-EUV NGL

October 28, 2011 - Stefan Wurm, director of SEMATECH’s lithography program, relayed highlights from last week’s EUV Symposium (Oct. 17-19 in Miami), including results in defects (mask blanks and substrates) and an update on SEMATECH’s EUV Mask Infrastructure (EMI) program.

AIMS

Zeiss presented on the repair strategies for EUV, where an aerial image measurement system (AIMS) for actinic inspection of reticle defects and repairs fits in. More notably, SEMATECH’s Michael Goldstein gave the first public account of the EUV Mask Infrastructure (EMI) program since the AIMS tool project kicked off in May — a "champion" multilayer mask blank with 41 pits and 10 particles, vs. a typical blank with 112 pits and 16 particles. Defect size/density requirements are about in step with the industry’s current improvement rate, but defect localization and pattern shifting "is a potential game-changer," he noted, and is required for any successful A-Bl equipment.

SEMATECH also reports that it is "seriously exploring" improving productivity for the AIMS and other actinic inspection tools by enabling a high-brightness source, which can be done within the EMI framework (and closely working with industry stakeholders).

Defects

IC makers (GlobalFoundries, IBM, Intel, Toshiba, TSMC) showed progress in developing defect avoidance and mitigation techniques that will allow them to use masks with a few remaining defects. Current mask defect levels are expected to support DRAM for pilot line operation soon while lower mask defect levels are required to meet logic/foundry requirements.

Amplitude defects are less frequent than phase defects but are present on every mask. He called for an industry spec roadmap for amplitude defects, and noted that SMT modeling and programmed amplitude-defect mask development has begun.

Preliminary substrate-defect roadmapping "appears to be overly conservative," though sensitivity requirements are likely below current inspection tool’s capabilities, Goldstein noted. Missed substrate defects can be picked up at ML blank inspection, but cost/cycle time impact might — or might not — be acceptable. Defect growth models are being calibrated so that substrate specs can be obtained by working back from the ML blank specs.

ML blank defect density today: 29 EUV mask blanks (Lasertec M7360) shows 2911 pits (~100/mask) and 484 particles (~17/mask). Cumulative blank yield, without localization and pattern shifting, shows 10% yield at >45nm sensitivity; 50% at 72nm; and 75% for 175nm threshold.

Potential issues seen cropping up at <16nm nodes include interference stack parameters, aperture, pupil fills, CRA, and defect types; SEMATECH and Lawrence Berkeley Labs are developing a system (SMT High-NA Actinic Reticle Review Project, or SHARP) to investigate blank and pattern mask patterns.

Resists

Several chemically amplified resist (CAR) materials achieving sub-20nm resolutions were demonstrated by member companies of SEMATECH’s Resist Program. This includes a 15nm half-pitch resolving CAR material (exposed on SEMATECH’s MET at Lawrence Berkeley National Laboratory by JSR), and a nanoparticle resist material demonstrating mid-20nm half-pitch resolution at excellent photosensitivity (developed in a SEMATECH research program with Cornell U. on SEMATECH’s MET in Albany, NY).

Presentations and priorities

Samsung’s Han-Ku Cho assessed the pilot-line readiness of EUV, and outlined the timetable and performance requirements for high-volume manufacturing for DRAM (in 2013).

Emily Gallagher from IBM won the best paper award for her presentation on EUV mask readiness ["EUV Masks: Ready or Not?"]. The best poster award winner was Hyung-Cheol Lee et al. from Hanyang U. for their work on "Realistic Thermal Effect of Extreme Ultraviolet Pellicle."

The EUVL Symposium Steering Committee identified three remaining focus areas that the industry needs to work on to enable EUVL manufacturing insertion:

  1. Long-term reliable source operation, 200W at IF;
  2. Mask yield & defect inspection/review infrastructure; and
  3. Resist resolution, sensitivity, and LER met simultaneously.

Next-gen litho not named EUV

Running simultaneously with the EUV Symposium was the Lithography Extensions Symposium, focusing on other patterning techniques to extend resolution capabilities more cost-effectively than, say, EUV.

Directed self-assembly (DSA) is making significant progress toward potential commercial application in semiconductor manufacturing. A wide variety of techniques including chemo-epitaxy, graphoepitaxy, and spin-on spacer, were all demonstrated as potential DSA based patterning approaches. Many resist and chemical suppliers (e.g., AZ, JSR, DOW) have active development activities underway both internally and with research partners.

Updating its work in DSA, IBM reported improvement in the patterning capability of existing lithography systems through contact hole rectification. Initial defectivity assessments indicate the current measured defectivity process is within the range of that initially seen during immersion lithography development.

Best paper award winner Cliff Henderson of Georgia Tech highlighted significant progress toward development of a mesoscale model that will help accurately predict material interactions needed to identify materials for DSA applications. Accurate predictive models will help design more effective DSA systems without time consuming experimentation.

Matt Malloy summarized SEMATECH’s Nanoimprint litho progress over the past three years, including data demonstrating overlay capability of 15nm and imprint process defectivity of <0.1>2. This highlights the potential for achieving imprint process defect levels commensurate with manufacturing requirements with additional industry effort.

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