October 21, 2011 — Imec engineers fabricated <1 picoliter sealed cavities directly on 200mm silicon wafers, using freestanding thin membranes of nanoporous anodic alumina (PAA). The thin-film vacuum wafer processing technology can package micro electro mechanical systems (MEMS) at the wafer level with strong, hermetic results.
Traditional thin-film wafer-level MEMS packaging techniques use lithography-defined release holes to remove the sacrificial layer and form the microcavity between the MEMS and the capping layer, potentially enabling sealing material to leak inside the cavity, onto the MEMS structures.
In Imec’s MEMS packaging method, nanopores serve as release etch holes. The cap layer with nanopores is a freestanding PAA membrane around 2-3µm thick. The cylindrical nanopores boast a 15-20nm diameter, creating an aspect ratio of >100. The high aspect ratio lets these holes close very rapidly during the first stage of sealing.
|Figure. Scanning electron microscopy (SEM) images of empty PAA-based thin-film packages, together with cross-section schematics (a-e) showing the process steps.|
First, a 3µm chemical vapor deposition (CVD) oxide sacrificial layer is deposited, patterned to obtain anchors and supporting pillars for the package. Next, a 1-1.5µm aluminium layer is sputtered. This layer is anodized, using a mask to define the microcavity areas. PAA membranes are typically 50% thicker than the original aluminium layer. Next, the sacrificial oxide layer under the membranes is etched away by exposing the wafer to HF vapour. Finally, the packages are sealed using a 4µm plasma-enhanced CVD (PECVD) silicon nitride layer.
Imec aimed to perform thin-film wafer-level MEMS packaging with reduced complexity. The wafer-level packaging (WLP) process takes place at low temperatures. It is reportedly simple, non-organic, and RF-compatible (the packages have a negligible impact on RF transmission for signal frequencies up to 67GHz). The dielectric caps are optically transparent, suiting optical MEMS applications.