IEDM 2011: Straining the limits of CMOS with Ge, III/V

 

Interest is picking up in Ge and III/V as high-mobility channel materials for scaling beyond the Si CMOS roadmap. IMEC researchers take a closer look at a new technique to selectively grow InP layers in submicron STI trenches on Si (001) substrates, using a thin Ge buffer. With "encouraging results" from Ge pMOS, they also describe the need for strain engineering to further boost performance, and new precursor/deposition methods for defect-free GeSn layers. [Paper #13.1, Advancing CMOS Beyond the Si Roadmap with Ge and III/V Devices" (Invited)]

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