STM completes 20nm chip tapeout with MENT design tools

November 7, 2011 – BUSINESS WIRE — Mentor Graphics Corporation (NASDAQ:MENT) completed a 20nm test chip tapeout with STMicroelectronics (NYSE:STM).

Mentor is pursuing a design-to-silicon framework for next-generation semiconductor nodes with the Olympus-SoC, Calibre and Tessent silicon test and yield analysis products. "The 20nm node has…new requirements including double patterning [lithography]," noted Pravin Madhani, general manager of the Mentor Place and Route Group. Process complexity, variability, large design sizes, low power requirements, and more are also considerations, added Philippe Magarshack, group VP at STMicroelectronics Technology Research and Development. The test chip was implemented using the Olympus-SoC place-and-route system, and verified using the Calibre nmDRC verification and double patterning platform (which is used by R&D teams at STMicroelectronics).

STM is a teaching customer and strategic investment partner in the DeCADE program for 20nm enablement. The joint-development project named DeCADE builds on advanced design technologies for system-on-chip (SoC) development. DeCADE reinforces the Crolles cooperative R&D cluster, which gathers partners that develop and enable low-power SoCs and value-added application-specific technologies, and is a project developed within the framework of the Nano2012 program. Nano2012 is a strategic R&D program, led by STMicroelectronics, which gathers research institutes and industrial partners and is supported by French national, regional and local authorities.

The Olympus-SoC place and route system is a complete netlist-to-GDSII system and is built on patented concurrent multi-corner multi-mode (MCMM) optimization, high capacity data model, advanced low power capabilities and integration with the Calibre platform for faster manufacturing closure. The OpenRouter architecture of the Olympus-SoC product enables native invocation of Calibre engines during design and uses the foundry signoff decks to ensure that the resulting layout is decomposable for multi-patterning, in addition to being DRC/LVS/DFM signoff clean.

Mentor Graphics Corporation (NASDAQ:MENT) makes electronic hardware and software design products and services. World Wide Web site: http://www.mentor.com/.

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