Copper interconnects: Process integration of iALD TaN

December 20, 2011 — Cu metallization is now widely used in both logic and memory devices. With the adoption of Cu metallization, metal barriers such as TaN are needed to enhance the adhesion of metal to the dielectric and prevent the diffusion of Cu through the dielectric. As the feature size continues to shrink, barrier thickness must be scaled to enable void-free Cu fill and allow the maximum volume of Cu in the feature to reduce resistance. Conformal TaN deposition can enable the reduction of metal barrier thickness while providing a continuous metal barrier film. PVD has been the mainstream technique for TaN deposition, but as feature size scales down, achieving good step coverage becomes more of a challenge.

ALD TaN has attracted much attention due to its capability to produce a conformal film with precise thickness control and high film density. In this study, we investigated the film characteristics and process integration of TaN produced using iALD. High-density TaN with low resistivity and excellent conformality is demonstrated with this process. Robust VSM, EM, and dielectric reliability are observed when iALD TaN is integrated into dual damascene interconnects.

Experimental

All iALD TaN process development work was conducted on an iALD chamber that was attached to a INOVA platform. The system also included a Remote Plasma Module (RPM) for reducing CuOx and cleaning etch residue prior to TaN deposition while minimizing the damage to ULK, as well as PVD Ta (IONX2) and Cu (IONFLO) modules. This configuration allowed all process steps to be performed without a vacuum break.

Dual damascene structures with 65nm technology node dimensions were used to investigate the electrical and reliability performance of the iALD TaN film. Low-k SiOC dielectric with k=3.0 was used as the main dielectric. A thin PVD barrier/seed process optimized for 45nm technology node was used as the reference control [1]. The test split included 10

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