IEDM interview: SEMATECH’s SILC ~10% and HKMG lifetime; ALD BeO a viable gate stack IPL solution

December 7, 2011 — SEMATECH’s director of front end processes, Paul Kirsch, discusses two of the consortium’s papers presented at IEEE’s International Electron Devices Meeting (IEDM) with Solid State Technology in a podcast interview (listen below).

In the first paper (#18.3: Improved high-k/metal gate lifetime via improved SILC understanding and mitigation), researchers identified key factors that impact stress-induced leakage current (SILC). This parameter is important because an increasing SILC can distort TDDB (time-dependent dielectric breakdown) lifetime extraction, noted the researchers. The group concluded that, “for accurate lifetime projections, the voltage-driven power law model proved more appropriate than the field-driven model.”


 

According to Kirsch, the key results included the finding that zirconium could be added to the bulk of the high-k dielectric, thereby improving the SILC by about 10% vs. the undoped control. “And the second result we found was that we could add fluorine to the stack, presumably ending up in the interfacial silicon oxide layer and improve the lifetime of the stack by about 10%,” he said.

Figure 1. SILC lifetime projection with and without added Zr. The DGE (inset) when Zr is incorporated is lower than in the control device, indicating a better quality bulk layer. SOURCE: Figure 19 from IEDM paper #18.3.
Figure 2. SILC lifetime projection with and without adding F. The difference in defect generation efficiency (DGE) (inset) of the two devices is negligible indicating a better quality IL. SOURCE: Figure 20 from IEDM paper #18.3.

A second paper, #28.2, entitled:  ALD beryllium oxide: novel barrier layer for high-performance gate stacks on Si and high mobility substrates, demonstrated that ALD BeO, when grown as a single crystal on Si and GaAs, is a viable gate stack IPL solution. The group found that, “BeO thin film minimizes a native oxide growth while providing exceptional electrical and reliability characteristics.”

Figure 3. TEM images of as-grown BeO on different substrates with high and low resolutions. SOURCE: Figure 5 from IEDM paper #28.2.

The team developed a new ALD precursor for Be and a new ALD process to put the BeO on both Si and on III/V semiconductors explained Kirsch in the podcast. “There is promising data both in terms of the physical properties of the material: including its bandgap, its ability to be grown epitaxially on semiconductors, as well as improvements in [interface trap density] (Dit) and mobility.”

Figure 4. Dit comparison between no interfacial passivation layer (IPL), Al2O3 and BeO IPL on the InGaAs substrate.  SOURCE: Figure 16 from IEDM paper #28.2.

“When we put the BeO on GaAs, we found that the Dit between the semiconductor and the BeO interface improved by about 2X vs. an aluminum oxide control, which is generally a standard dielectric to put on a III-V semiconductor,” said Kirsch. “Furthermore, the mobility improved about 2X when BeO was put on a III-V semiconductor relative to the aluminum oxide control."

Figure 5. Mobility comparison between bulk Al2O3 and BeO on InGaAs MOSFETs. SOURCE: Figure 17 from IEDM paper #28.2.

 

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