22nm node semiconductors: Technical forecasts

January 3, 2012 — Solid State Technology asked top analysts and technologists to provide insights on the transition to 22nm semiconductor devices. Read through all the forecasts, or click by topic, from chip design to lithography, CMP, and materials, to the packaging side of the equation.

Check out the first article, from Dean Freeman of Gartner Inc:
Semiconductor process technology challenges at 22nm

And a design perspective, from Gary Smith of Gary Smith EDA:
At 22nm, leave chip layout to the experts

Defect discussion, with Howard Ko of Synopsys:
First order effects at 22nm

The lithography point of view, with Aki Fujimura, D2S:
Mask-wafer double simulation: A new lithography requirement at 22nm

What 22nm means for the packaging providers, from E. Jan Vardaman, TechSearch International:
22nm requires foundry-to-packaging-house cooperation

An in-depth look at gate stacks and materials, with Mohith Verghese, ASM America:
Strained silicon and HKMG take the stage at 22nm

The role of a mid-node, TSVs, and 450mm at 22nm, with Art Zafiropoulo, Ultratech:
Will 22nm need a mid-node?

The CMP point of view, from Michael A. Fury, Techcet Group:
Startups pave the way to CMP at 22nm

Driving technologies for 22nm lithography, from Franklin Kalk, Toppan Photomasks:
20nm mask technology relies on SMO and DPT

How 3D IC fits into the 22nm equation, with Paul Lindner, EV Group:
3D integration key to 22nm semiconductor devices


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