ISSCC round-up: 2.5D packaging for IVRs, smallest NAND flash chip, more

February 22, 2012 — International Solid-State Circuits Conference (ISSCC) is going on now, February 19-23, in San Francisco, CA. The conference gathers semiconductor design and device architecture presentations from research firms like imec to chip companies like IBM. Following are some highlighted presentations.

On-chip voltage regulator
University-research consortium Semiconductor Research Corporation (SRC) and Columbia University showcased integrated voltage regulators (IVR) that feature energy densities more than 10x that of present state-of-art inductors. By introducing an unprecedented combination of magnetic materials, chip-stacking design and a 2.5D chip packaging process, the team from Columbia University (funded in part by the SRC) demonstrated a new IVR solution developed with a research team from IBM (SRC member). The technology can reduce power consumption, by 10-20% in a typical US data center, for example. The power converters integrated onto the same chip, or into the same package, as microprocessors "significantly improves computational performance per watt of power consumed," said Professor Ken Shepard, lead researcher for the team at Columbia. The researchers provided all of the traditional advantages of a switched-inductor converter in a form factor that is small enough to integrate on-chip. Another SRC member, Intel Corporation, also has been engaged actively in research in this area. More information about the research is published in “A 2.5D Integrated Voltage Regulator Using Coupled Magnetic Core Inductors on Silicon Interposer Delivering 10.8A/mm2,” presented at ISSCC at the session on Advances in Heterogeneous Integration. The paper is co-authored by Noah Sturcken, Michele Petracca, Ryan Davies, Ioannis Kymissis, Luca P. Carloni and Kenneth L. Shepard from Columbia, Angel V. Peterchev from Duke and Eugene J. O’Sullivan, Naigang Wang, Philipp Herget, Bucknell Webb, Lubomyr T. Romankiw, Robert Fontana, Gary M. Decad and William J. Gallagher from IBM. Learn more at

THz circuits from CMOS silicon fab
SRC and UT Dallas showed that circuits operating at the terahertz (THz) range can be affordably manufactured (hundreds of dollars instead of hundreds of thousands of dollars) in complementary metal-oxide semiconductor (CMOS) silicon, potentially creating new application sectors, including defense, medical, industrial process control and public and industrial safety. In contrast with x-ray, THz is intrinsically safe, non-destructive and non-invasive. With the cost-effective manufacturing development, THz can become accessible for use in everyday products. UT Dallas showed that a THz receiver can be manufactured affordably, using standard Schottky diodes in 130nm CMOS with higher cut-off frequency than MOS transistors. More information about the research is published in “280GHz and 860GHz Image Sensors Using Schottky-Barrier Diodes in 0.13µm Digital CMOS,” presented at ISSCC. The research is funded through SRC and performed at the RF and THz laboratory of Texas Analog Center of Excellence at UT Dallas. The paper is co-authored by Ruonan Han, a former student of Professor O, and Yaming Zhang, Yongwan Kim, Dae-Yeon Kim and Sam Shichijo at UT Dallas. More information at

Smallest NAND Flash
Flash memory maker SanDisk Corporation (NASDAQ:SNDK) highlighted the smallest 128Gb NAND flash memory chip currently in production, on a 170mm2 silicon die, targeting smartphone and tablet integration. SanDisk built the 128Gb NAND flash memory chip on its 19nm process technology, using its three-bit per cell (X3) technology. At 19nm, SanDisk is deploying its 9th generation of multi-level cell (MLC) NAND products and fifth generation of X3 technology. The 128Gb semiconductor device has X3 write performance of 18MB/s using SanDisk’s advanced all bit line (ABL) architecture. The 128Gb NAND flash memory chip was developed jointly by teams from SanDisk and Toshiba at SanDisk’s Milpitas campus. The effort was led by Yan Li, director of Memory Design at SanDisk. More information at

First use of resonant clock mesh technology in volume ICs
AMD implemented Cyclos Semiconductor’s low-power semiconductor intellectual property (IP) in the AMD x86 core for inclusion in Opteron server processors and client Accelerated Processing Units (APUs). The adoption of the Cyclos resonant clock mesh IP will reduce power consumption. AMD’s 4+ GHz x86-64 core code-named “Piledriver” employs resonant clocking to reduce clock distribution power up to 24% while maintaining the low clock-skew target required by high-performance processors. Piledriver is the first volume production-enabled implementation of resonant clock mesh technology, with no increase in silicon area or changes to the chip manufacturing process. Cyclos resonant clock mesh technology uses on-chip inductors to create an electric pendulum, or tank circuit, formed by the large capacitance of the clock mesh in parallel with the Cyclos inductors. The Cyclos inductors and clock control circuits recycle the clock power instead of dissipating it on every clock cycle. More information at and

Higher-power, more-efficient SAR ADC
imec and Renesas Electronics Corporation reported a successive-approximation register (SAR) analog to digital converter (ADC) with improved power efficiency and speed, targeting wireless receivers for next-generation high-bandwidth standards. The new SAR ADC architecture is much faster than traditional chips, with small form factor and low power usage (1.7mWatt), achieving high resolution (11b). The fully dynamic, two-step interleaved pipelined SAR ADC achieves 10fJoule per conversion step power efficiency at a sampling speed as high as 250MSamples/s. The ADC prototype has been manufactured in 40nm CMOS with a core chip area of 0.066mm2.

Also at ISSCC, imec and Renesas Electronics present a new way to connect the ADC architecture with the complete radio architecture. To improve the power efficiency of the total receiver system, and avoid issues related to large input capacitors in a voltage-domain ADC system, a 3.2-51.2m Siemens current domain variable-gain transconductor (VGA) was used to drive a charge-domain SAR ADC with no overhead. A 10b 10-80MSamples/s VGA-ADC prototype in 40nm CMOS achieves 70dB DR while consuming less than 5.45mA from a 1.1V supply.

Wireless sensor, organic electronics work
imec and Holst Centre are presenting 14 papers on low-power design for wireless communication and wireless sensor networks, and organic electronics. In one, Imec and Holst Centre, in collaboration with Panasonic, announced a 2.3/2.4GHz transmitter for wireless sensor applications compliant with 4 wireless standards (IEEE802.15.6/4/4g and Bluetooth Low Energy), fabricated in a 90nm CMOS process. The transistor consumes 5.4mW from a 1.2V supply (2.7nJ/bit) at 0dBm output, 3-5x times more power-efficient than today’s Bluetooth-LE solutions. Imec’s new transmitter saves at least 75% of power consumption by replacing several power-hungry analog blocks with digitally-assisted circuits. With the SD−DPA for the generation of the time-variant signal envelope, it is also the first published ultralow-power 2.4GHz-ISM band IEEE802.15.6-compliant transceiver. Check out the list and major highlights here.

Want to see your ISSCC presentation highlighted here?
Send an email to digital media editor Meredith Courtemanche at with your presentation details.

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