Semiconductor metrology beyond 22nm: Defect inspection and review

In this three-part series, SEMATECH’s authors cover metrology for FinFETs (Read Part 1) and 3D memory devices (Read Part 2), and defect detection capabilities at 22nm. The series appears in the upcoming March 2012 issue of Solid State Technology, along with other metrology-focused pieces from KLA-Tencor and Entegris. Subscribe to Solid State Technology magazine here.

February 23, 2012 — Future challenges for semiconductor defect metrology go beyond merely extending the capability of current technologies to meet International Technology Roadmap for Semiconductors (ITRS) requirements [8]. In recent years, the yield enhancement ITRS chapter has shown that the semiconductor industry consistently arrives at each new technology node without a long-term solution that combines defect sensitivity and throughput requirements at either development, ramp-up, or HVM phases.[8]   Both defect inspection and review are approaching their fundamental limits, which cannot be easily circumvented with gradual improvements on workhorse toolsets [13].

Figure 3. There is a single defect in this 22nm-node SRAM array. Can you find it?

In the specific case of inspection, optical simulations show that the defect contrast signal decays aggressively beyond the 22nm node, and predict that deep ultraviolet (DUV) bright field tools are likely to lack useable signal at or beyond the 11nm node. Wavelength scaling is not expected to provide an acceptable solution, prompting the need to seek alternative technologies that rely on different contrast mechanisms that may bridge this gap: interferometric (phase shift signal) [14], near-field (sub-wavelength resolution), or fast probe microscopy [15]. This path-finding effort will have a steep learning curve in terms of the application space for these techniques and the engineering to translate them into manufacturing-worthy tools. An alternative path to achieve sub-11 nm inspection capability may be electron beam (e-beam) inspection. In this case, the challenge is not resolution but increasing the system throughput by several orders of magnitude, which will most likely require a breakthrough in e-beam column parallelization. Early efforts are currently driven by lithography needs, but could benefit the inspection application space [16].

After defects are found (see Figure 3 for an example), they must be identified and sourced to maintain yield, requiring increasing amounts of off-line lab analysis. As features shrink, the X-ray interaction volume used in EDX for in situ defect analysis is becoming larger than the sizes of critical defects. The only solution appears to be an explosive growth in the workload of the TEM characterization lab. The limitation to TEM is not capability but throughput. TEM requires extensive, time-consuming sample preparation. Moreover, the microscope itself is a complex device that traditionally requires hours of work by a highly skilled operator to obtain good results. The solution therefore is to focus on both problems. To this end, SEMATECH is working with leading suppliers to develop faster sample preparation techniques, by both optimizing existing technologies and testing novel methods such as plasma focused ion beam (FIB) and laser-based milling. SEMATECH is also working in cooperation with its strategic partners to develop higher speed TEM imaging capabilities. This includes testing the latest generation of high sensitivity and high throughput windowless detector systems and developing automated image setup and metrology on critical dimension scanning/tunneling (CD-S/TEM) systems.

Figure 4. Sample image of a high-speed EDX element map taken on a SEMATECH FinFET sample. Total collection time was 4 minutes.

Conclusion
As device technology transitions from traditional scaling to new architectures, new application needs are driving metrology towards evolutionary and revolutionary shifts in technologies and methodologies. Adaptation to new tool paradigms, enhancements of existing technologies, and productivity innovations will be critical to maintain process control and high yield in the coming technology generations. The SEMATECH Advanced Metrology Program is well positioned to develop solutions to address the measurement challenges of next generation devices.

Miss Parts 1 and 2? Check them out:

References
[1] Doyle, B. et al., “Tri-Gate Fully-Depleted CMOS Transistors: Fabrication, Design and Layout,” Symposium on VLSl Technology Digest of Technical Papers, pp. 133-134 (2003).

[2] Vaid, A., et al. “A holistic metrology approach: hybrid metrology utilizing scatterometry, CD-AFM, and CD-SEM.” Metrology, Inspection, and Process Control for Microlithography XXV. Proceedings of the SPIE, Volume 7971, pp. 797103-797103-20 (2011).

[3] Wang, C., Choi, K., Chen, Y. Price, J., Ho, D., Jones, R., Soles, C., Lin, E., Wu, W.L., Bunday, B. “Nonplanar high-k dielectric thickness measurements using CD-SAXS.” Proc. SPIE, v. 7272, pp 72722M (2009).

[4] De Martino, A., et al., “Comparison of Spectroscopic Mueller Polarimetry, Standard Scatterometry and Real Space Imaging Techniques (SEM and 3D-AFM) for Dimensional Characterization of Periodic Structures,” Proc. of SPIE Vol. 6922, 69221P (2008).

[5] Larson, D.J., and Kelly, T. F., “Nanoscale Analysis of Materials using a Local-Electrode Atom Probe,” Microscopy and Microanalysis Volume: 20, Issue: 3, pp: 59-62 (2006).

[6] Mody, J. et al., “Dopant and Carrier Profiling in FinFET-Based Devices with Sub-Nanometer Resolution,” 2010 Symposium on VLSI Technology, pp. 155-156

Abraham Arceo is a metrology development engineer at SEMATECH Advanced Metrology group. For the past three years he has been involved in film and defect inspection metrology development.

Benjamin Bunday is the project manager of CD Metrology and a Senior Member Technical Staff at SEMATECH (Albany, NY, USA). For ten years he has led SEMATECH/ISMI’s CD-SEM and OCD benchmarking, advanced CD technology evaluation and development efforts, and SEMATECH’s Advanced CD Metrology Advisory Group (AMAG).

Aaron Cordes is a research engineer for Sematech in Albany doing work on AFM, TEM, and focused ion beam metrology. He is also a PhD student with SUNY Albany’s College of Nanoscale Science and Engineering.

Victor Vartanian is a metrology engineer at SEMATECH in Albany, New York. Before coming to SEMATECH, he worked at Freescale Semiconductor in Austin, Texas, where he worked on applications of strained silicon to advanced transistor design and analytical applications of FTIR and mass spectrometry to environmental issues in semiconductor manufacturing and in process optimization.

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