SPIE Advanced Lithography: Intel’s, TSMC’s tool roadmap takeaways

February 15, 2012 — After attending SPIE Advanced Lithography, this week in San Jose, CA, Barclays Capital came away with a lower lithography tool shipments forecast, more hope for extreme ultraviolet (EUV) lithography, and expectations of a litho buying spree at Intel. Following is their wrap-up from the conference.

Moore’s Law, particularly as it relates to cost, is proving a challenge to uphold. Qualcomm’s presentation showed that Moore’s Law (on the economic side) is being threatened from scaling requirements/adoption of new materials. The traditional cost drop of 30% per annum is expected to slow/level off at the 20nm node. Someone — equipment vendor, foundry partner, fabless chipmaker, OEM, and/or the end consumer — will feel it in their wallet.

While memory chip makers have adopted self-aligned double-patterning (SADP) — a less-lithography-intensive approach — logic/foundry will adopt litho-etch-litho-etch (LELE) at advanced nodes. Overlay will be critical as well at smaller nodes. To print an advanced logic chip at the 22/20nm node, the chipmaker will have roughly ~55 single exposures or 40% increase in litho layers (all else being equal).

Mix-and-match overlay solutions (ArF Immersion and ArF Dry toolsets, and EUV) will become more important than single tool overlay requirements as the semiconductor industry scales down to smaller nodes.

Barclays notes that, 5 years ago, "nobody believed EUV would work." Today, the call for EUV is louder. Different semiconductor manufacturers are taking different approaches to patterning at 14nm: TSMC plans to implement high-volume EUV, but Intel expects to use double patterning, not switching to EUVL or quadruple patterning until the 10nm node.

Also read: Intel, Samsung, TSMC semiconductor capex in 2012 signal market dominance

TSMC received its first 3100 tool in 2H11, with the tool now up and running and through source upgrade, showing 10W EUV power today. The company expects the 3300 high-volume scanner to be delivered by the end of CY12. TSMC highlighted source power, mask inspection/mask repair, and mask handling as areas for improvement in EUV technology.

Intel plans to move double patterning at 14nm into production in 2013 and also expects to initiate an EUV pilot line (initially using Intel 3100 tool) at the same time. At 10nm, Intel likely will use complimentary patterning (i.e. mix and match of EUV and QP/ArF immersion techniques). With Intel moving to high-volume 14nm production in 2013 and critical layers using ArF Dry and immersion tools set to double from 23 to 46, Barclays anticipates a meaningful step up in wafer-fab equipment (WFE) spend from Intel in 2013, particularly for litho – look for order pickup late 2012.

Barclays updated its immersion lithography tool forecast: Expect 82 immersion shipments in 2012 (down from 87). Memomry makers will take 32 shipments (down from 41) with fewer to Rexchip/Inotera in DRAM, as well as incrementally fewer to IMFS, Samsung, Hynix, and Toshiba. Logic houses will take 20 (old 21) with 1 more to IBM and 2 fewer to Intel. Foundries will install 30 (up from 25), with 1 more to both UMC and SMIC, with incrementals from Samsung LSI and TSM.

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