ISSCC from a memory analyst’s view

March 2, 2012 — The International Solid State Circuits Conference (ISSCC) took place in San Francisco the week of February 20. The best and brightest minds in semiconductors met to share the results of the past year’s research and development efforts. From a memory perspective, this show contained some highly interesting presentations.

Also read: ISSCC round-up – 2.5D packaging for IVRs, smallest NAND flash chip, more

Eli Harari keynote
The three-day conference began with a keynote speech by Eli Harari, retired chairman of SanDisk. He recounted the history of flash memory, weaving in other related insights.

Although both NOR and NAND flash are now a part of everyday life, Harari reminded us that Toshiba’s Fujio Matsuoka invented NAND flash only 25 years ago, in 1987, three years after he invented NOR flash. NAND yielded a memory cell very close to the theoretical smallest size of 4f² but had some very undesirable side effects of serial access and high error rates, so it needed to be coupled with the intelligence to get past these limitations. Harari noted that Matsuoka is an “Out of the Box” thinker.

Harari went on to say that nobody expected for NAND flash to work and looked upon it as a “crazy idea.” It was a solution looking for a problem. One very significant concern was that the memory chip couldn’t stand on its own as did most other memory chips, and what Harari calls “Assisted NAND” was needed. This was a NAND chip coupled with a controller to perform error correction, wear leveling, and bad block management.

When SanDisk started to use NAND, the controller overhead was so great the company was ridiculed by its competitors. SanDisk stood its ground and, eventually, assisted NAND prevailed.

As a dramatic demonstration, Harari pointed out that, using today’s NAND flash technology, a 64GB microSD card provides about 6 Terabytes per cubic inch. He told the audience that this bit density would allow the entire US Library of Congress to be contained in about 1.5 cubic inches (55cc).

Harari thanked Toshiba for not abandoning NAND in its early days when few believed in the semiconductor technology. He remarked that the Toshiba/SanDisk joint venture has been one of the most successful in the history of semiconductors, and now supplies roughly 40% of the world’s NAND flash.

The presentation lit upon several historical landmarks and a number of humorous twists, the most important of which were the life lessons from an undisputed leader in the industry: Stick to your convictions, especially when your gut instinct tells you that you’re right. Perseverance in the face of naysayers really does pay off.

Harari’s keynote had the rapt attention of everyone in the room.

DRAM session
Samsung showed a 39nm 4Gb DRAM in a presentation that highlighted the clock circuitry. A very sophisticated DLL was used that had a switchable linear or digital delay line depending on the clock frequency. Internal error correction included parity on the address and command lines and a cyclic redundancy code (CRC) on the data. The company also presented an LP-DDR3 device that offers double the bandwidth of LP-DDR2 at the same voltage. The process for this part was not disclosed.

Hynix presented a 1.2V 38nm 2Gb DDR4 DRAM with a die size of only 43.15mm². The power consumption was roughly 50% lower than that of the chip’s DDR3 counterpart, even though the new chip’s core frequency is the same as the DDR3 part. Hynix also presented a DDR3 DRAM that uses a 23nm process to produce a 30.9mm² chip — the smallest die size ever reported for this density. Hynix brought also a special clocking circuit for through silicon via (TSV) DRAM interfaces that uses sophisticated logic to align the clock with data from all the chips in a multi-chip stack.

Although this was not the nonvolatile session, Samsung presented a phase-change random access memory (PRAM) that had a high bandwidth despite its large cell size of 7f². Novel approaches shortened the program time of this 29nm process chip.

There were two university papers, from Keio University and the University of West Virginia. Keio showed an innovative non-contact memory bus configured to eliminate capacitive loading concerns, and University of Virginia communicated over a wired channel using two different frequency bands to support simultaneous transmission and reception of data.

Nonvolatile memory (NVM) advances
Both Toshiba and SanDisk presented papers on the two companies’ 128Gb NAND chip that uses three-bit cells and a 19nm process to achieve the smallest die size (170.6 mm²) for a chip of this density. This device uses some exotic techniques, like air gaps to lower the bitline RC time constant, and an internal temperature sensor, both of which help to keep the speed similar to devices processed on less aggressive geometries.

The University of Tokyo presented a very sophisticated SSD controller that not only corrected NAND bit errors based on the chip’s layout, but also used special reprogramming techniques to restore bits to their original value after they may have been corrupted by adjacent cell disturbances.

The Korea Advanced Institute of Science & Technology (KAIST) also presented a controller that used a high-speed multithreaded encoder/decoder with multiple ECC engines to provide error correction and flash management at enterprise SSD speeds.

Samsung presented a "sub-20nm" NAND flash, but the speaker was caught in a difficult position by the corporate dictum that Samsung’s management would not allow him to disclose the true process geometry while audience members demanded it. This caused an unusual disquiet in the room.

Panasonic spoke about a crosspoint resisitance RAM (ReRAM) that solved many difficulties through the novel use of a very simple back-to-back Zener diode structure to select the cells while allowing the bidirectional current flow required to achieve cell programming. More detail on this approach is given at http://thememoryguy.com/how-do-you-make-an-reram-work/

TSMC also presented an ReRAM, focusing on the sub-0.5 Volt sense amplifier — a first for a memory chip.

Conclusion
As happens every year, ISSCC included several intriguing papers that showed not only directions that the market is heading, but also the challenges confronting chip makers as we approach the end of scaling for both NAND and DRAM.

Jim Handy is an analyst at Objective Analysis, which offers third-party independent market research and data for the semiconductor industry and investors in the semiconductor industry. He has over 35 years in the electronics industry including 20 years as a leading semiconductor and SSD industry analyst. Early in his career he held marketing and design positions at leading semiconductor suppliers including Intel, National Semiconductor, and Infineon. Learn more at http://www.objective-analysis.com/

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