The 2012 Common Platform Technology Forum took place March 14 at the Santa Clara Convention Center, with registration topping 1200 attendees by noon. The Common Platform is a Samsung /IBM/GlobalFoundries foundry services entity created to provide a common design space with an assured production capability.
The meeting kicked off with Ana Hunter, Samsung’s foundry business VP. The Common Platform had its roots in 65nm, and is presently working with 20nm gate-last and 14nm FinFET. Pre-revenue investment in the 20nm to 14nm range approaches $10B, with $1-2B in process development, $250M in IP & design libraries, $100M in chip design and $7B in fab construction.
Gary Patton, VP of SRDC at IBM, gave the first keynote with prognostication on the kind of technology development that is in the pipeline beyond traditional CMOS scaling. We are presently in the 3D decade, both in terms of 3D transistor design and 3D packaging integration. Next will be the decade of nanotechnology materials, in which the critical device dimensions do not depend on photolithography. Long-term R&D for this coming decade is already underway, as an extremely long lead time is required for commercialization to manufacturing. In 2011 IBM broke its own US patent record with 6,000 filings, a position it has held for 19 straight years. He hopes EUV will be ready for 10nm, “but we have a dual path.” At 10nm, EUV will provide a bump in k1 factor from 0.15 to 0.55, better that we enjoyed at 90nm. The scanner still needs a 10x improvement in light power, but additional work is needed in photoresist materials and mask fabrication and inspection technology. A new EUV Center of Excellence at Albany CNSE is expected to be operational later this year. Below 80nm, resist development is focusing on directed self-assembly (DSA) of block copolymers. Presently, the 22/20nm work is being done in East Fishkill; 14/10nm at Albany; and 7nm & beyond at Yorktown Research. Fully depleted device structures are the recurring theme going forward. CNT devices provide advantages over FinFETs in terms an order of magnitude reduction in power consumption at the same operating frequency, or an order of magnitude increase in frequency at the same power. With these innovations in design constructs and materials, Gary noted that the transistors are still much more amenable to scaling than interconnects, in which RC performance and structural reliability in both the conductors and the insulators doth protest mightily with scaling. Photonic interconnects on chip continues to be an area of intense development, moving now from fundamental unit performance demonstrations to system integration. The packaging concepts that he reviewed, while challenging, we consistent with advanced packaging concepts that have been progressing over the past five years. TSV is currently in volume manufacturing for power system chips. For stacking large DRAM chips on top of high performance MPU, he expects TSV to be in production within 2 years.
Subi Kengeri, head of the advanced architecture development group, filled in for GlobalFoundries CTO Gregg Bartlett to discuss the convergence of consumer mobility applications enabled by semiconductor technology advances. Foundries are a 300mm leading edge business growing at 15% CAGR. Since 90nm, the time between design start and tape out has been extending as design complexity increases. Design cost has been increasing at a 25% CAGR, whereas fab cost has been increasing at 18%, albeit a much larger number. Smart mobile computing is starting to move into the design driver seat that has up to now been occupied by MPU and GPU functions. Gate last HkMG at 20nm has been selected to meet these needs for 3rd generation HkMG FinFET mobile devices. At 14nm FinFET, you need 100 WPH (wafers per hour) throughput with EUV to break even with 193i with multiple patterning; 180 WPH provides a compelling advantage for EUV.
Jong Shik Yoon, Senior VP Semiconductor R&D at Samsung, spoke on opportunities and challenges in 3D device integration. SOI FinFETs were pioneered by IBM, while Samsung & Intel led the development of bulk FinFETs; the Common Platform supports bulk FinFET. SOI FinFET is used by IBM for server and specialty mobile applications. CNT FET work has been going on at Samsung as well.
Simon Segars, EVP & GM of the ARM Physical IP Division, wrapped up the morning with the fabless design and manufacturing implementation perspective. Industry drivers today are mobile computing, servers and the “internet of things.” Lower cost entry level smart phones represent another billion unit market globally. Mobile networks require about 1 server for every 600 phones, which puts the server demand into perspective, particularly as servers alone become a more significant percentage of world power consumption (still single digits for now). Global internet mobile traffic for 2015 will be about 966 exabytes (that’s a whole lot of gigabytes…). Simon is confident that the collaboration infrastructure that has gotten them to 20nm is extendable to 14nm.
A panel discussion featuring R&D leaders from the 3 Common Platform partners, ARM and CNSE on the R&D pipeline for future semiconductor technology innovation followed lunch. Michael Liehr, VP Research at CNSE pointed out several ways in which the fab there operates like an industrial site, with professors leading engineering teams that function as much like an IDM process development group as a graduate student research group. GlobalFoundries in Malta, NY is currently running 32nm production and 20nm full flow qualification. Work on DSA for photolithography started at IBM in 2000 and is still not ready for prime time. Similarly, copper interconnect development work started at IBM in 1984 and didn’t go into production until 1997, and even then came as a surprise to many outsiders. This is indeed a very long development pipeline.
Rama Divakaruni, IBM Chief Technologist, and Lars Liebmann, IBM Distinguished Engineer, opened a technology session on 14nm technology development with a review of the grand challenges. EUV shows up as a fuzzy transition some time in 2H14 shortly before the 14nm production ramp begins. Development started about 30 years ago in the national labs, but they hope to be able to support integrated process flow development at Albany by YE13. This seems to add gravitas to Gary Patton’s expressed hope that it will actually be ready for 10nm. Triple patterning with 198i is proposed for M1 to maintain design protocols on a path that will provide for a relatively easy return to the EUV goal of single exposure for M1. When pressed for a volume production implementation of EUV, Lars admitted ‘not before 2015’ but could be no more specific.
Yongjoo Jeon, Samsung’s Director of Foundry Technical Marketing gave an overview of their technology offerings at 20nm. Samsung has two versions of the 20nm platform: 20LPE available June 2012 and 20LPM, scheduled for full production May 2013. The 20LPM will use double patterning for isolation, via 0 and minimum pitch M1; both are HkMG gate last. Their 20nm devices are currently 10% below target for DC performance and 20% below target for AC performance, but the root causes are known and the program is considered on schedule to meet its release dates.
Mukesh Khare, Director of Semiconductor Technology at IBM Research, described the innovation pipeline beyond 14nm. Technology elements will include strain, HkMG and FinFET variations to leverage recent innovations, but nanowires will lead the way to a brave new world. We’ve transitioned to a domain in which scaling leads to degradation rather than improvement; new materials and process innovation are required in its place. A silicon nanowire is thought to represent the ultimate extension of the fin structure. The game is already afoot for applying strain to an individual nanowire. Alternative channel material candidates include III-Vs for nFET and Ge and high % Si-Ge for pFET, though challenges remain for silicon integration and contact resistance. Carbon electronics will provide extraordinary carrier mobility and extremely long carrier mean free paths. IBM’s 40nm epitaxial graphene transistor on SiC still holds the RF performance record at 280GHz. Polymer DSA is IBM’s pipeline alternative to EUV. The technology has already been used in the dielectrics used in air gap interconnects. The photoresist analog holds the promise of providing ‘pitch in a bottle.’ The double entendre will be better appreciated on days when it does not work. In combination with 193i, DSA has been used to produce 25nm line/space pairs with excellent line edge roughness.
Michael A. Fury is a Director & Senior Technology Analyst at Techcet Group.