ST-Ericsson adopts FDSOI from Soitec

March 12, 2012 — ST-Ericsson, wireless semiconductor company, selected planar fully depleted silicon on insulator (FD-SOI) technology from Soitec (Euronext), semiconductor materials maker, for use in future mobile platforms.

Soitec’s substrates have an extremely thin top layer that predefines critical characteristics of the fully depleted transistor: an extremely thin layer of silicon over a buried oxide (BOx) layer. FDSOI offers higher performance without a strain on battery life, noted Louis Tannyeres, chief chip architect, ST-Ericsson. "The results of our work with STMicroelectronics on FD-SOI have demonstrated that this technology is able to deliver these benefits in a cost-effective manner."

STMicroelectronics, Leti, Soitec, and IBM have collaborated for several years on FDSOI, demonstrating its benefits at 28nm and smaller nodes. FDSOI solves the scaling, leakage and variability issues that are associated with shrinking CMOS technology starting at 28nm, notes Soitec.

Also read: Soitec’s extreme SOI: Scalable below 14nm

Soitec’s FDSOI wafers will support NovaThor performance at as much as 35% reduced power consumption — four additional hours of high-speed Web browsing or as much as a day of additional battery life in typical consumer use. Peak performance of processors built on fully depleted wafers can experience up to 60% increase, with design optimization.

A fully depleted transistor architecture on FDSOI still allows semiconductor companies to leverage existing design and manufacturing capabilities, said Paul Boudre, chief operating officer of Soitec, calling the deal with ST-Ericsson the "first step toward fully depleted planar CMOS technology." Fully depleted wafers are processed with standard fab tools sharing many process steps with a conventional, low-power bulk CMOS process. They save 10% of the steps required to fabricate the chips, Soitec reports.

FDSOI "essentially provides the fully depleted transistor benefits of FinFETs on a planar conventional technology, while allowing advanced back bias techniques, which are not available with FinFETs," in wireless applications, said Joël Hartmann, STMicroelectronics assistant general manager, Technology R&D.

Soitec generates and manufactures semiconductor materials for energy and electronics applications. For more information, visit:

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