Georgia Tech targets thin 3D packaging with new consortium

April 11, 2012 — Georgia Institute of Technology (Georgia Tech) Packaging Research Center (GT-PRC) proposes a new consortium on 3D semiconductor packaging called 3D ThinPack (THInPack) for ultra-miniaturized 3D heterogeneous, RF, digital and power modules in partnership with global companies.

The goal is ultra-miniaturized heterogeneous sub-systems created using 3D integration of multiple ultra-slim packages with embedded thin active or passive components. Within 2 years, the consortium will demonstrate a 4-package stack within ~1mm thickness.

GT-PRC has been developing ultra-miniaturized embedded MEMS, actives, and passives (EMAP) technology through a global industry consortium of about 15 semiconductor, package and supply-chain companies with chip-last (CL) interconnections but with chip-first benefits to demonstrate ultra-miniaturized modules with digital, RF, analog, MEMS and sensor functions. GT-PRC has demonstrated ultra-thin organic substrates, fine-pitch copper-to-copper (Cu-Cu) interconnections, low-temperature bonding with high assembly throughput and prototype functional module demonstration of digital Si and RF GaAs die embedding.

Building on these advances, GT-PRC

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