Soitec’s fully depleted (FD) semiconductor product roadmap

April 17, 2012 — Soitec (Euronext), semiconductor materials supplier, released its fully depleted (FD) product roadmap, comprising two products designed for planar and three-dimensional (FinFET) approaches to building semiconductor transistors. Soitec also announced research and other activities dedicated to further boosting transistor performance, both silicon-based and with new materials.

FD wafers from Soitec pre-integrate critical characteristics of the transistor within the wafer structure. They can be used as a “low-risk migration” product for 28nm to 10nm nodes, the company reports.

Soitec’s product lines support the industry’s FD International Technology Roadmap for Semiconductors (ITRS), speeding time-to-market and lowering chipmakers’ overall manufacturing costs.

Soitec’s FD-2D product line enables a planar approach to fully depleted silicon transistors as early as the 28nm node, in which chipmakers can continue to leverage their existing designs and process technologies. FD-2D enables immediate gains in performance and energy efficiency for mobile and consumer multimedia chips. The top silicon layer of Soitec’s FD-2D wafers is ultra-thin and ultra-uniform, making it possible to achieve planar fully depleted transistors with a silicon thickness that may be as low as 5nm under the gate. Between this top layer and the underlying silicon base is an ultra-thin layer of buried oxide (BOX), initially at 25nm thick. Future generations can leverage even thinner BOX layers down, to 10nm thick, providing a path for planar transistor scalability down to 14nm for mobile devices. Silicon thickness uniformity in volume production of planar fully depleted technology is critical for best results. Soitec’s FD-2D wafers have a top silicon thickness that is controlled to within just a few atomic layers. Leveraging the inherent accuracy of Soitec’s Smart Cut process, silicon uniformity across a full 300mm-diameter wafer can be as good as 3.2 Angstroms. The first sample ICs with this fully depleted architecture are expected at the end of 2012. At 28nm, compared to conventional technology, the energy consumption of chips can be reduced by up to 40 percent, and the maximum operating frequency of the processors these chips embed can be improved by 40 percent or more with design optimizations. Power supply requirements are below 0.7V.

The company’s FD-3D product line facilitates the introduction of three-dimensional (FinFET) architectures with reduced time and investment, and drives substantial simplifications in the transistor fabrication process, targeting nodes below 20nm. The top layer of Soitec’s FD-3D wafers is a thin layer of silicon over a buried oxide layer with a thickness defined according to customers’ needs. The silicon top layer predefines the fin height and the BOX layer provides built-in intrinsic isolation. Compared to using conventional bulk silicon starting wafers, FD-3D results in fewer challenging steps in the FinFET fabrication process, driving lower capital expenditures and operating expenses, higher production throughput and, ultimately, lower cost. In addition, these benefits translate to shorter process development learning cycles, fewer industrialization challenges and faster time to market for FinFET technology into the mainstream foundry market. Experts estimate FD-3D substrates offer a potential gain of as much as one year with respect to the trajectory possible using conventional bulk silicon substrates. The benefits of predefining fin height and isolation at the substrate level translate to better manufacturability and less process variability, leading to better overall performance at the chip level.

“FD-2D enables immediate and significant performance leaps, while FD-3D makes FinFET a reality for the entire industry at accelerated schedules and reduced risk,” said Paul Boudre, COO, Soitec.

Soitec also is working actively to research new ways to further boost transistor performance, both silicon-based and with new materials. To continue pushing the performance of silicon CMOS, Soitec will add “strained silicon” to both its FD-2D and FD-3D product lines, with pre-production expected no later than 2014. With this solution, the crystalline structure of the silicon layer, in which transistors will subsequently be built, is modified by Soitec during fabrication of the starting wafers. This results in significantly improved electron mobility and higher maximum operating frequency for the transistors and circuits.

Looking further, several new CMOS technology options are being researched in the semiconductor industry for introduction beyond the 14nm node. The main candidates include incorporation of high-mobility materials such as germanium (Ge) or III-V materials, as well as new transistor architectures such as nano-wires. Soitec is actively engaged in different R&D programs and has a number of joint development programs with partners to enhance its product lines and propose the best products to meet the needs of the industry.

Soitec is also anticipating the transition from 300mm to 450mm wafers through in-house and collaborative R&D programs to support the industry roadmap. Both the FD-2D and FD-3D offerings are fully scalable to 450mm.

Soitec makes semiconductor materials for energy and electronic applications. For more information, visit

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