Advantest DRAM test system clocks 8Gbps test speed on every pin

May 14, 2012 — Advantest Corporation (TSE:6857, NYSE:ATE) uncrated the next-generation high-speed memory test system, T5511, offering 8Gbps test speed. Designed for dynamic random access memory (DRAM) test, the T5511 performs tests on diverse chip generations and DRAM architectures. It can be deployed from R&D through to volume production.

Ultra-fast GDDR5-SDRAM chips used for graphics need functions such as clock training and cyclic redundancy check (CRC) to ensure their reliability and high-speed performance. DDR4-SDRAM for servers and clients will soon achieve twice the bandwidth of mainstream DDR3-SDRAM and functionality equal to GDDR5. In the mobile and graphics segments, bus widths of x32 and x64 are now mainstream; wide I/O DRAMs with a 256-bit wide interface will soon be standardized.

The T5511’s 8Gbps test speed (4GHz) and ±40ps timing accuracy enable GDDR5-SDRAM device test. Since all the system’s test pins support 8Gbps, no reduction in parallelism occurs when operating at high speed. Parallel test capacity is 256 (x8 I/O). Clock training functionality is built into T5511’s hardware for testing new DDR4-SDRAM and GDDR5-SDRAM devices, keeping throughput higher than software-based clock training designs, Advantest reports. The T5511 also features a hardware CRC code generator function for these components, generating CRC codes automatically.

The T5511 runs Advantest’s “Future Suite” tester operating system, including the entire library of program data created for T55xx series test systems.

System configurations range from 384 pins for R&D use through 6,144 pins for volume production. Users can configure a test tool to move from lab to fab as needed.

Advantest (NYSE:ATE) manufactures electronic measuring instruments, automatic test equipment, and electron beam lithography systems. Learn more at www.advantest.co.jp.

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