Directed self-assembly lithography research yields contact holes on semiconductor wafer May 28, 2012 — Stanford University researchers, sponsored by Semiconductor Research Corporation (SRC), a university-research consortium for semiconductors and related technologies, have created contact hole patterns for logic and memory semiconductors using a next-generation directed self-assembly (DSA) lithography process. “This is the first time that the critical contact holes have been placed with DSA for standard cell libraries of VLSI chips,” said H.-S. Philip Wong, lead researcher at Stanford for the SRC-guided research. Applying a relatively simple combination of chemical and thermal processes to create their DSA method for making circuits at 22nm, the nanofabrication technique could enable pattern etching for next-generation chips down to 14nm. Figure. Researchers first use a layout for 22nm SRAM contacts in the top layer. Through conventional lithography, a guiding template is fabricated, shown on the second layer. Application of a block copolymer solution leads to a self-assembled circuit contact pattern in the third layer. Traditional lithography methods lose accuracy as transistor nodes get smaller. This new work is reportedly a more affordable and environmentally friendly path to fabricating leading-edge semiconductor devices, and possibly other nano technologies. DSA created a composed pattern of real circuits, not test structures, Wong reported. The irregular nature of Stanford’s DSA could heal imperfections in the pattern and maintain higher resolution and finer features on the wafer than by any other viable alternative, Wong added. The new DSA process starts with covering a wafer surface with a block copolymer film. Common lithographic techniques were used to carve impressions into the wafer surface, producing a pattern of irregularly placed indentations that serve as templates to guide movement of molecules of the block copolymer into self-assembled configurations. By varying the shape and size of the guiding templates, manufacturers can space holes more closely. In order to provide the safest solvents for use in the coating and etching process, the researchers selected polyethylene glycol monomethyl ether acetate (PGMEA) as a healthier and more effective alternative compared to other options. Important next steps remain for the research. Among those is engagement with electronic design automation experts for the purpose of developing software and tools that will enable circuit designers to specify where the holes are to be located on the wafer. This resource for chip designers will allow them to plan without the distraction of where to place the guiding templates, providing the industry with another advantage in addition to the delay of investment in next-generation lithography tools. Further details about the research and its conclusions are available at http://onlinelibrary.wiley.com/doi/10.1002/adma.201200265/pdf. SRC defines industry needs, invests in and manages the research that gives its members a competitive advantage in the dynamic global marketplace. For more information, visit www.src.org. This work is additionally sponsored by the Division of Civil, Mechanical and Manufacturing Innovation (CMMI) of the National Science Foundation. Visit the Semiconductors Channel of Solid State Technology!