May 30, 2012 – BUSINESS WIRE — Semiconductor direct bonding technology provider Ziptronix Inc. is helping a 3D memory device maker replace standard die stacking with its DBI wafer-stacking technology. Memory stacking can enable higher memory density in a given footprint, and the wafer-level stacking technology could significantly reduce packaging cost for the 3D architecture.
Traditional die stacking requires die thinning and thinned-die handling and development of reliable interconnect processes. Ziptronix DBI combines proprietary wafer-level low-temperature oxide bonding and interconnection. It creates extremely strong low-stress bonds, allowing wafers to be processed and thinned after bonding, eliminating the need to handle thinned wafers and/or dies. Interconnect density and alignment accuracy are high, and the device profile is kept low, Ziptronix notes. The process is compatible with damascene interconnect processing, and various test and repair strategies.
DBI is used for backside imaging (BSI) sensors, where Ziptronix reports that it delivers cost savings of up to 80% over copper thermo-compression bonding. The new collaboration is founded on Ziptronix DBI