The 15th IITC (International Interconnect Technology Conference) opened Monday, June 4 at the Doubletree Hotel in San Jose, CA with about 230 engineers, scientists and technologists in attendance under a light drizzle. Recurring themes this year were variations on 3D and TSV, novel systems and packaging, and back end memory.
Mike Mayberry, VP Components Research at Intel, delivered the opening keynote address with prognostication for what lies ahead for devices and interconnects. The traditional trio of smaller, faster, cheaper is joined by longer battery life. An asymmetric device, tunneling FET (TFET), is one option that may be able to deliver 8x performance over CMOS while operating at very low voltages. Interconnect shrinkage brings us to the physical limitations of barrier vs. copper volume for reliability vs. conductivity, as illustrated in this 10nm copper trench.
But while there are physical limits, Mayberry proffered that the correct answer to “where will it end” is “when we run out of ideas.” One new idea is the notion of stacking devices themselves, rather than remaining constrained to a single layer of silicon. This can provide a device density gain of 30%-50%. New architectures like associative memory will be fostered by new ways of using consumer devices, such as context-sensitive device response. For example, minimizing distractions while you are driving, or silencing your hilarious ring tone during business meetings, might be desirable capabilities to have built in. “If you only look for better versions of what you have today, you are going to miss opportunities,” he said. On-chip optical interconnects are likely to be limited in scope due to density and power considerations.
Soo-Hyun Kim of Yeungnam U (Korea) gave an invited talk on ALD Ru with organometallic precursors for copper seed layer and capacitor electrodes. Rapid nucleation was achieved using three different zero-valent Ru compounds reacting with molecular O2. Nucleation begins within the first 2-3 cycles, with thin film coalescence coming in the 50-60 cycle range. In addition, nucleus density is 1.5-2 orders of magnitude higher with these precursors compared to a more traditional Ru(EtCp)2. Good conformality was shown up to AR 32 at 225°C deposition temperature.
Theo Frot of IBM Almaden Research described some approaches to protecting porous low-κ dielectrics from plasma and CMP damage. The post-porosity plasma protection strategy yields the best results on a variety of dielectrics ranging from κ 2.4 to κ 1.8 in DHF wet etch and O2 plasma-induced damage (PID) tests.
One of the observed fringe benefits of this process strategy is a lower rate of post-CMP delamination. The original κ 2.0 value was confirmed following integration in a single damascene layer test structure.
Christopher Wilson of IMEC integrated a κ 2.3 spin-on dielectric for sub-28nm technology using EUV lithography. Structures were fabricated at a 40nm half pitch and post-etch dielectric constant was restored with a He/H2 plasma treatment that resulted in a 13% improvement in RC characteristics. Single damascene and dual damascene dielectric stacks are shown in the figure.
TDDB did not degrade as the spaces between the 40nm trenches were scaled from 90nm to 40nm.
YH Wu of TSMC described the use of an uncured ELK material as a CMP stop layer. Following CMP, the ELK porogen is activated to form the low-κ dielectric, resulting in a net smaller shift in κ. Integration schemes with and without the uncured ELK layer had comparable leakage, but the uncured ELK layer increases line-to-line capacitance by 7% before curing. After curing, the capacitance penalty was eliminated. Benefits of the stop layer include an improvement of copper thickness control across the wafer from 11% to 4%.
Chih-Chao Yang of IBM Albany Research showed the use of Co films as Cu capping layers. Better TDDB results with no dependence on Co thickness were observed with an in-situ process, in which the Cu oxide removal prior to Co deposition is conducted in a single reaction chamber with no air exposure between steps.
Jürgen Wolf of Fraunhofer IZM-ASSID described the outlook for silicon interposers with integrated TSVs for 3D SiP integration. Process schemes are designed with an eye toward leveraging WLP designs and manufacturing methods. Several temporary wafer bonding technologies are included in the mix to accommodate the in-process handling of extremely thin wafers for WLP. SnAg and SnAgCu alloys for Pb-free reflow soldering to Au bumps have been found to be adequate up to this point in the development process.
Jinho An of Samsung spoke about controlling extrusion defects in Cu TSV through annealing process conditions and structural design factors. TSV diameter has the largest effect on the tendency to extrude. Carbon and sulfur impurities affect the copper grain size, which in turn is inversely related to percent extrusion.
Ashish Dembla of Georgia Tech described a scheme for fine pitch (35µm) high AR (18:1) TSV integration in silicon micropin-fin heat sinks. The microfluidic prototype structure shown could handle a power density of 100 W/cm2 with a resulting junction temperature <50°C and a pressure drop of 83kPa. The silicon pins were fabricated with a cluster of copper TSVs inside each pin to enhance thermal transport as well as to provide the TSV functionality.
Michael Van Buskirk of Adesto Technologies gave an invited talk on a scalable, low power, high performance resistive memory technology platform called conductive bridging RAM (CBRAM). The device shown consists of a W cathode, Ag anode and GeS2 solid electrolyte switching layer. The operating principle is based on the formation of a conductive silver dendrite between the electrodes, with conductivity increasing the longer the ON switching current is left on. This makes is conceivable to have multiple ON states in a single device. A 1Mb serial EEPROM/Flash combination product has been integrated into a 130nm Cu BEOL design and is commercially available. Cross-contamination concerns about the introduction of Ag into the fab were handled with minor modification of the same protocols required for Cu. The device has demonstrated an endurance of 100k write cycles with 10 year data retention at 70°C.
Jonggi Kim of Yonsei U (Korea) described the switching mechanism of another resistive switching device, this one based on the redox migration of oxygen ions in HfO2 between Ni/Ti and Pt electrodes.
Honggun Kim of Samsung R&D presented a novel flowable CVD process technology for sub-20nm interlayer dielectrics. Process conditions made it possible to eliminate the Si3N4 oxidation diffusion barrier, reducing the bit-line loading capacitance by 15%. Gap fill for AR 40:1 has been demonstrated with peak process temperature <500°C.
S. Maîtrejean of CEA Leti talked about the challenges in phase change memories from a materials and process perspective. The addition of carbon to PVD GeTe correlated well with MOCVD GeTe with residual carbon. A confined device structure performed better in terms of switching time and ΔR than the earlier plug designs with an unconstrained PCM layer.