SEMICON West preview: MEMS manufacturing changes with HV consumer apps

The high-volume consumer applications driving the fast growth of the micro electro mechanical system (MEMS) market are putting new demands on MEMS development and manufacturing. Goals? Get products to market faster, make them easier to integrate into systems, reduce die size; and better control processes to bring down costs. That’s attracted investment from the supply chain in a range of new solutions, from innovative new process technologies and tools developed specifically for MEMS sector needs, to more efficient integrated design software.

June 27, 2012 — The MEMS sector is poised for a multiyear period of steady double digit growth, with 20% average annual increases in unit demand, as systems makers find ever more uses for low cost, easy-to-integrate silicon sensors and actuators, reports Jean Christophe Eloy, founder and CEO of Yole Développement, driving the MEMS market to double, to reach $21 billion by 2017. Volume consumer markets are driving much of this growth, as consumer applications accounted for more than 50% of total MEMS industry revenue in 2011. And that’s turning the once artisanal niche into a high volume production business, and bringing rapid technology change, with a push for speeding time to market, sharply scaling down die size, increasing integration of multiple sensors into combination units, and bringing more packaging value to the wafer level. “2011 has been the year of the transition of the MEMS market into big business with wide diffusion,” says Eloy. “But the ability of MEMS manufacturers to continue to scale size and cost, and to simplify development and system integration will directly impact the growth of MEMS business.”

Figure. Common model of an accelerometer being used as a block in the control system design stage. A common model reduces design iterations by allowing teams to easily move between design stages to identify failures and optimize the system. SOURCE: Coventor.


Meeting time-to-market needs with more efficient design tools
While decreasing time to market and cost reduction have always been key drivers, the short product cycle times associated with mobile consumer devices have forever changed the industry. “Development time is now measured in months, not years,” notes Mattan Kamon, Coventor’s Principal Technologist. “However, design is still mostly done using traditional research approaches, where different models are used at different stages of the design, costing valuable time.” Coventor’s approach accelerates MEMS product development by using a common model for all stages of design. An engineering team can use a single model to develop and optimize the MEMS device concept, tune and validate the design using 3D simulations, perform system simulation together with the ASIC, investigate packaging effects, and optimize yield. All of these steps can be performed using a single model, enabling MEMS teams to easily move back and forth between the design stages, identify failure mechanisms, and optimize the system.

Kamon argues this methodology has the accuracy to address integration effects and can optimize the nominal behavior and the range of behavior across a wafer due to fabrication variations. Coventor’s approach couples a library of high-order finite element models specialized for MEMS with judicious use of low-order finite element simulations, and uses the same simulators, namely MATLAB, Simulink, and Cadence Virtuoso, that are most widely used for analog/mixed-signal design. This holds potential for a MEMS verification flow that closely parallels the verification flow for analog/mixed signal design, and paves the way for a fabless MEMS industry complete with MEMS design kits (MDKs).

New processes to make low-cost cavities without etching

Finnish startup Scannano proposes that MEMS die size and cost could be significantly reduced, and performance improved, by creating sealed cavities in devices by using a controlled diffusion process, instead of by the traditional method of etching sacrificial layers and bonding on a cap wafer.

Following on from research with Nokia’s Research Center and Cambridge’s Cavendish Laboratory, company founders Andrei Pavlov and Yelena Pavlova came up with the idea of shrinking away buried layers in a device by through diffusion to create a vacuum gap, allowing the use of standard CMOS materials and equipment. The process deposits a proprietary multi-layer diffusion material, builds the MEMS structure over it, and then submits it to a series of processing steps to shrink the diffusion material. This creates a very accurate sealed vacuum cavity of the desired dimensions and configuration. “The gaps can be from a few nanometers to up to a micron deep, and can be vertical or at an angle, or multiple gaps could surround a structure, opening up the possibility of new types of MEMS designs,” says Pavlov. He also claims that shrinking features to 50-100nm can also reduce operating voltage to only a few volts and reduce heat, while the very smooth surfaces help to improve sensitivity, signal-to-noise ratio and performance.

The first application for Scannano’s Deep Vacuum Gap Technology is a tunable capacitor and switch for multiband tunability for mobile phones, under development with STMicroelectronics and tentatively targeted for initial trial production on a CMOS line by the end of the year. The new device adjusts operating frequencies by changing capacitance through moving membrane-like MEMS structures, created by adjusting gap dimensions above and below the membrane. Pavlov says work with ST has been progressing for about a year, and is now moving towards final device design and testing. Scannano is also working with other European CMOS device manufacturers to develop sensors for the automotive market, monolithically integrated with the ASIC in their CMOS fabs.

Figure. MEMS structures with aspect ratios of >100:1. SOURCE: Applied Materials.

Volume markets attract investment in dedicated MEMS processes and tools

Fast growing MEMS volumes have also attracted the attention of more semiconductor players, including equipment giant Applied Materials. Applied has invested aggressively in development of new film and process technologies to support current and future generations of MEMS production at ≤200mm wafer sizes, focusing on shrinking die size, improving throughput, and integrating MEMS processes into CMOS fabs, says Mike Rosa, MEMS product line manager. This includes DRIE technology critical for both increased productivity and process flexibility as next generation MEMS devices enter the sub-micron range of critical dimensions, with aspect ratios of >100:1 (see the figure above).

Applied Materials is also working on modifying its PVD and CVD equipment to make a variety of enabling films of new materials for MEMS, including thick (>20µm), low temperature CVD films (SiO2, SiGe, etc.); and PVD films such as magnetically aligned NiFe, high uniformity AlN and thick Al.

Tool vendors will need to be increasingly attuned to the MEMS device capability and technology requirements of their customers’ customers, the fabless device designers and systems companies, notes Rosa. “In the MEMS industry there is no traditional roadmap, like the ITRS, to define the future,” he says. “It will take a much more collaborative effort by all parties — tool vendors, device manufacturers, and end-market product developers — to define and deliver the next generation MEMS designs that are destined for the newest ‘next big thing’ products.”

Also focusing on enabling tools for next generation MEMS is Nikon, with a new stepper with a large depth of focus specifically for the 200mm MEMS market. Though MEMS makers have traditionally used lower cost aligners to make their relatively large patterns, now finer features and tighter design rules may increasingly require the higher resolution and better alignment accuracy of steppers. But IC steppers are typically expensive and not well suited to the extreme topographies of MEMS. This Mini Stepper has ≤0.35µm overlay accuracy and resolution to 2µm, and depth of focus capabilities up to 26 µm for the thick resists and deformed substrates typical of MEMS, reports Junpei Fukui, Nikon Engineering assistant manager. It also offer flexible alignment to compensate for MEMS’ process-induced distortions, as well as alignment by pattern matching and backside marks.

These and other speakers including IDT, Hanking Electronics, Teledyne DALSA, Micralyne and NIST discuss solutions for growing the MEMS sector to the next level at SEMICON West, July 10 -12 in San Francisco. See for the complete agenda, and to register.

Read on for a SEMICON West preview from Doe on collaboration in the MEMS ecosystem.


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