July 10, 2012 — Imec Technology Forum (ITF) took place just before SEMICON West 2012 opened in San Francisco, CA. ITF, held at the Marriott Marquis, focused on advanced semiconductor architectures and process technologies, with an additional impetus placed on the healthcare/medical industry.
Luc Van den hove, president and CEO, imec, spoke with Solid State Technology’s digital media editor, Meredith Courtemanche, covering imec’s major announcements and research presentations to take place during SEMICON West 2012. Summaries of imec’s presentations follow the video.
To enhance the advanced metal-high-k gate stack for next-generation logic devices, imec successfully demonstrated higher-k dielectric with Replacement Metal Gate (Metal-Gate-Last) transistors that achieved 200-1000x reduction in gate leakage relative to leading-edge logic devices in the industry with HfO2 high-k gate dielectric. To address the process control and scalability of the replacement metal gate for nano-scale devices, imec achieved tight electrical distribution down to 20nm gate length through detailed process optimizations. By providing fundamental insights into work-function influences due to metal intermixing in aggressively-scaled metal gates, imec’s research addresses an important source of variability in advanced transistors.
Imec has also invested significant effort in the development of 3D FinFET devices and high-k metal gate over the last 10 years. In the 14nm platform, these features will be combined with the next generation of stress engineering. For the next node — 10nm — we will replace the silicon channel in the FinFET devices with high-mobility materials. And for the nodes beyond 10nm, we are evaluating two possible device routes: tunnelFETs and junction-less nanowires.
In NAND Flash memory, imec further develops hybrid floating gate architecture, scaling this architecture to 15nm and beyond. Beyond 10nm, the main emerging technology is resistive RAM (RRAM). We’ve made significant progress on RRAM: imec recently announced 10nm functional RRAM, made significant improvements in performance and reliability of RRAM cells by process improvements and clever stack-engineering, and increased fundamental understanding of RRAM process technology.
In DRAM memory, imec is helping to scale MIMcap technology with a focus on materials. Beyond MIMcap, SST-MRAM is the leading candidate on the industry’s emerging DRAM roadmaps. Therefore, in November 2011, imec launched a program on SST-MRAM, for stand-alone DRAM as well as replacement of embedded SRAM.
To enable further scaling, imec is focusing on the extreme ultraviolet (EUV) lithography pre-production readiness and on extending immersion lithography using advanced patterning integration schemes. To further push the limits of 193nm immersion lithography and overcome some of the critical concerns for EUV lithography, imec implemented 300mm fab-compatible Directed Self-Assembly (DSA) process line all-under-one-roof in imec’s 300mm cleanroom fab. Imec’s DSA collaboration aims to address the critical hurdles to take DSA from the academic lab-scale environment into high-volume manufacturing.
The focus of imec’s nano-interconnect program is technology scaling including materials, process, integration, reliability and system aspects.
Imec is investigating half pitch (hp) multiple patterning techniques in combination with immersion lithography, and EUV lithography with single or double patterning techniques.
To improve the mechanical stability and low-damage patterning and integration schemes to reduce the k value, imec studies post-deposition techniques and the impact on performance and reliability.
To avoid wire resistance increase, imec explores metallization using new barrier and seed materials as well as novel deposition and filling techniques such as manganese and ruthenium based metallization, atomic layer deposition and chemical vapor deposition techniques.
3D integration enables system scaling through 3D chip stacking with through-silicon-vias. Imec’s 3D integration processes are completely executed on 300mm. All processes and flows are tested on functional circuit demonstration vehicles. As part of the INSITE program, imec proposes flows for modeling, simulation, design and testing of 3D systems.
Imec’s early-version PDK (process development kit) for 14nm logic chips is the industry’s first to address the 14nm technology node. It targets the introduction of a number of new key technologies, such as FinFET technology and EUV lithography. With this PDK release, imec leads the way to an industry-standard 14nm PDK. In addition, the PDK anticipates the introduction of a number of new technologies at the 14nm node. The main example is the use of FinFET transistors, which have a larger drive per unit footprint and higher performance at low supply voltages compared to the traditional planar technologies. Evolutions of this PDK will gradually also introduce the use of high-mobility channel materials. The PDK includes elements of both immersion- and EUV lithography, opening the way for a gradual transition from 193nm immersion to EUV lithography.
Future systems will become increasingly dependent on a high input/output bandwidth. Not only between systems, but also between the chips in a system, or even between the cores on a chip.
With optical components, it is possible to build interconnects that have the required bandwidth without consuming more power. Silicon photonics allows fabricating optical components with state-of-the-art semiconductor equipment, using the same processes and tools as for the fabrication of state-of-the-art chips.
At Semicon West, imec will announce the first important results of its industrial affiliation program (IIAP) on high-bandwidth optical input/output. This program is working towards a manufacturable solution for achieving high-bandwidth communication by modeling and engineering optical solutions for high-bandwidth communication between CMOS chips.