Real-time monitoring slashes water and energy usage in semiconductor manufacturing on 300mm and 450mm wafers July 23, 2012 — Researchers sponsored by Semiconductor Research Corporation (SRC), a leading university-research consortium for semiconductors and related technologies, developed new sensor-based metrology technology that can significantly reduce water and related energy usage during semiconductor manufacturing. The sensor-based real-time monitoring approach showed 30% less water and energy used for ultra-clean chip production. The SRC Engineering Research Center (ERC) for Environmentally Benign Semiconductor Manufacturing team at the University of Arizona (UA) calls this “the most significant metrology improvements for the rinse and cleaning of wafers in more than a decade.” Figure. In-situ monitors provide unprecedented control of water and chemical usage during surface preparation for silicon wafers. Highly sensitive sensors, like those shown in this micrograph of a sensing channel, can reduce the amount of resources needed for the cleaning of surfaces. Surface preparation, when semiconductor wafers are cleaned, rinsed, and dried to prevent defects between various front end of line and back end of line (FEOL/BEOL) steps, is one of the largest water-consuming processes in semiconductor manufacturing. The International Technology Roadmap for Semiconductors (ITRS) identifies lower resource utilization at current and future fabrication steps among its goals. Also read: Semiconductor fabs use significantly less energy today, but work remains from ISMI. The ERC team’s real-time monitoring approach is applicable to current cleaning processes for 300mm silicon wafers, and the gain is expected to be especially beneficial when the industry transitions to 450mm wafers. At 450mm, chipmakers will need to clean and prep a wafer surface that is more than twice the size of current state-of-art wafers. Current surface preparation practices are recipe-based and not controlled with real-time, in-line monitoring of the process steps. Surface prep is carried out without feedback or control, with a large cushion of safety to overcome lack of regulation. This sizeable safety factor creates unnecessary waste of chemicals, water and energy. “The challenge is how to balance a minimal application of precious resources with the grave risk of allowing contamination to occur, which can kill huge investments made elsewhere in the fabrication process,” said Dr. Steve Hillenius, executive vice president for SRC. The next step is to commercialize the monitoring technology, said Farhang Shadman, lead researcher and the ERC director at UA for the SRC-funded research. Semiconductor equipment and manufacturing companies, as well as other industries that use ultra-clean for planar or patterned surfaces and small structures could use the real-time metrology technology to improve resource management. Examples include optics, optoelectronics, and flat panel display (FPD) makers. For more information about the research, please visit http://dx.doi.org/10.1109/TSM.2010.2089542. Contributors for the joint effort include K. Dhane, J. Han, J. Yan, O. Mahdavi, D. Zamani, B. Vermeire and F. Shadman. SRC defines industry needs, invests in and manages the research that gives its members a competitive advantage in the dynamic global marketplace. For more information, visit www.src.org. Visit the Semiconductors Channel of Solid State Technology!