In the third installment in a series called Process Watch, the authors discuss some of the challenges of 450mm wafers. Authored by experts at KLA-Tencor, Process Watch articles focus on novel process control solutions.
August 2, 2012 — Chip manufacturers need wafers that are both bigger and better: bigger to help achieve cost targets through gains in manufacturing efficiency, and better to help reach device performance targets through the time-honored path of the pattern shrink. Our industry leaders have announced plans for pilot lines producing devices with sub-20nm linewidths on 450mm wafers, beginning in 2014 or 2015.
In the meantime, wafer manufacturers need to figure out how to make these giant wafers. The increased time required to grow the huge silicon ingot and then to cool it down under conditions optimized for crystal quality raises the risk of defects in the silicon crystal significantly.1 Polishing the surface uniformly and without microscratches requires new equipment and consumables. New cleaning equipment and processes must be developed. Also, 450mm wafers are proportionally thinner than 300mm wafers — which means they are more likely to deform during processing or handling. Such deformation can induce slip lines — crystal lattice defects similar to geological slip lines after an earthquake — around the edge of the large wafer. Crystal-originated pits (COPs), particles, slip lines, microscratches and cleaning residues all can interfere with one or more of the tightly-controlled processes that comprise the early steps of building a semiconductor device.
Printing smaller patterns necessitates tighter specs on many aspects of the wafer — regardless of wafer size. Because 450mm wafers will be used for sub-20nm lithography, their flatness and surface roughness must be very well controlled. Gradual changes in the shape of the wafer surface can be corrected by the scanner during patterning, but the wafer must be reasonably planar across the reticle field. More abrupt changes in the shape of the wafer surface may not be correctable; this is termed higher-order shape. Uncorrectable higher-order shape can displace the pattern, resulting in misalignment (overlay error) between layers — or it can cause defocus errors that affect the critical dimension (CD) of the printed structures. Higher-order shape can also interfere with film uniformity during chemical-mechanical polish (CMP) processes. Any of these errors can result in electrical problems affecting the device’s reliability, performance or yield.
450mm wafers have a higher number of edge die — notoriously the lowest yielding die on the wafer. The shape of the edge (“Edge Roll-Off” or ERO) can affect CD during patterning of edge die. Defectivity at and near the edge of 450mm wafers is typically higher, and will need to be very carefully monitored.
In essence, substrate manufacturers need to make much larger wafers with surfaces even more perfect than they are now: truly bigger and better wafers. The impact of the surface quality, defectivity, flatness and ERO of 450mm wafers is considerable: With more than twice the number of die as a 300mm wafer, every 450mm wafer is extremely valuable. And just to add an extra challenge, some industry pioneers have announced that they will manufacture devices on 450mm epi wafers — adding the complexity of an epitaxial silicon layer, with its slightly increased surface roughness, stress-induced warp and unique epi defects. There is also interest in validation of 450mm silicon-on-insulator (SOI) technology.
Bare-wafer metrology and defect inspection play key and early parts in enabling wafer, equipment and chip manufacturers to develop and control their sub-20nm processes on 450mm wafers. These tools need the sensitivity to meet sub-20nm node requirements, and the ability to handle 450mm wafers with reliability and speed. Sub-20nm inspection sensitivity is enabled by deep-ultraviolet (DUV) technology and high-resolution haze mapping, technology that was pioneered recently on 300mm wafers by the latest-generation surface inspection systems. The images below show examples of surface defects, polishing marks and cleaning residues revealed on 450mm wafers by the latest inspection technology. These images are visually interesting, but indicative of the early stages of the manufacturing process; images of wafers meeting chip manufacturing specs would look nearly uniform. High resolution surfaces images such as these are a quick and intuitive tool for identifying the source of the defect, so that the issue can be remedied immediately, before additional time and materials are consumed.
Rebecca Howland, Ph.D., is a senior director in the corporate group and Amir Azordegan, Ph.D., is a senior director in the Surfscan/ADE division at KLA-Tencor.
1. See for example, “Technical challenges in the development of next generation wafers.”.
Check out other Process Watch articles: “The Dangerous Disappearing Defect,” “Skewing the Defect Pareto,” “Bigger and Better Wafers,” “Taming the Overlay Beast,” “A Clean, Well-Lighted Reticle,” “Breaking Parametric Correlation,” “Cycle Time’s Paradoxical Relationship to Yield,” and “The Gleam of Well-Polished Sapphire.”
Authored by experts at KLA-Tencor, Process Watch articles focus on novel process control solutions for chip manufacturing at the leading edge.