Karen Savala, president, SEMI Americas
August 10, 2012 — This year at the SEMICON West press conference, I presented on “Supply Chain Readiness in an Era of Accelerated Change” and I’d like to summarize that presentation for you. The talk centered on the increasing capital and technology requirements of advanced semiconductor production and the pressures this creates on the supply chain. The structure of the industry is rapidly changing — and how it will respond to the simultaneous challenges of Moore’s Law scaling, 450mm wafer production, 3D-ICs, and industry consolidation is very much unknown. Much of this uncertainty is reflected in what we call “supply chain readiness.”
|Never before has the industry faced greater economic and technological uncertainty. The industry is consolidating, with fewer leading edge chip makers and fewer leading edge suppliers. The technical challenges are increasing as geometric scaling and Moore’s Law now must be accomplished with rising process engineering complexity — particularly in the areas of EUV lithography, 3D-IC chip packages and 450mm wafers.|
The economic and technical challenges of today’s environment will have an impact on supply chain readiness. In the past, the size and scope of the industry supported a vibrant supply chain of start-ups, innovators at the leading edge, brilliant fast-followers, and a variety of technology and process specialists.
Today, the supply chain is dominated by several large OEM companies who rely upon a global ecosystem of technology subsystem and component firms. As process engineering becomes more complex at leading-edge nodes, the readiness of the supply chain to deliver advanced, integrated solutions becomes less certain.
Photolithography systems are among the most complex and expensive machines on the planet. They are also the most important tool to maintain the pace of Moore’s Law. From advanced light sources from Cymer to highly engineered optics and lenses from Carl Zeiss, approximately 90% of an ASML lithography system comes from external suppliers. EUV systems are currently shipping, but as you know, they do not meet the required wafers-per-hour throughout for high-volume production. Consequently, EUV is being deployed in conjunction with immersion lithography, directed assembly and other options. The node at which EUV fully enters mass production is still uncertain — certainly below 20nm, perhaps at the 16 nm node, possibly at 8nm.
To alleviate some of this uncertainty, both Intel and TSMC have made significant investments in ASML to support EUV development and help accelerate the introduction of 450mm systems. While this massive infusion of cash will assure a common mission between these key industry players, how it will impact next generation mask infrastructure has yet to be seen.
In mask readiness, EUV mask blanks are an order of magnitude more complex than today’s conventional mask blanks. Spectacular work has been accomplished to improve yield and reduce defects on these new systems.
Today, according to SEMATECH, mask performance is sufficient to meet the needs of memory, but still short on meeting the requirements for logic. More importantly, as this chart shows, you’ll see that a significant gap between EUV mask blank demand and supply capacity currently exists. Uncertain EUV insertion will make investment difficult for suppliers to address this capacity shortfall before full production is assured. This uncertainty may also threaten production volume availability for EUV resists.
3D-IC is another area of dramatic and uncertain change lies in the area of 3D-IC stacked chips. Given their potential for smaller form factors, increased performance, and reduced cost and power consumption, 3D-IC technologies are now enabling the next generation of advanced semiconductor packaging. Already, 2.5D approaches using silicon interposers to provide wide IO bandwidth and denser packaging have been introduced, but many manufacturing and collaboration barriers remain before widespread commercialization.
3D integration using through-silicon vias promise a fundamental shift for current multi-chip integration and packaging approaches. But cost-effective, high-volume manufacturing will be difficult to achieve without standardized equipment, mat䁥rials, and processes.
With many advanced packaging processes taking place on the semiconductor wafer, the traditional supply chain of “front-end fab at the foundry” and “back-end fab at the packaging and test house” is at risk of falling apart. TSMC has been clear about their vision. They want an expanded role in the industry to implement — not just wafer foundry services — but 3D integration as well, including thinning, bumping and assembly.
While the business models sort themselves out, there remain technology challenges and process flow uncertainty. Chips-on-substrate, chips-on-wafer and chip-on-chip all remain viable options.
Currently, there are no collaboration models to solve this foundry-OSAT-IDM and fabless chip matrix for complex, multi-chip packages. SEMI standards are addressing many supply chain, equipment and materials issues. However, market demand and business models must continue to sort themselves out before 3D chip stacking can widely penetrate the industry.
450mm Wafer Transition
The most expensive semiconductor industry technology transition in history will occur with the transition to 450mm wafers. R&D costs alone are estimated to rise between $8 and $40 billion, depending on the efficiency with which the transition is coordinated. The high end of this estimate represents a level of investment that is equivalent to what the entire industry spent on advanced process development over the past five years. These costs will be incurred concurrently with other major technical challenges in the industry, including the move to 3D transistor structures, and EUV and 3D stacked chips already mentioned. The recent investments in ASML by Intel and TSMC reflect just how much the industry will be changed by 450mm development requirements.
Currently, the Global 450 Consortium, or G450C, with members from Intel, IBM, Global Foundries, TSMC, and Samsung, is in the process of constructing and equipping a 450 pilot line in New York. G450C has said that it expects the line to complete by mid- 2013 to early 2014. The business model to equip this pilot line is unlike anything we’ve seen before — in this industry or elsewhere! The pilot line will feature approximately 50 tool types, most if not all, from no more than two vendors. Performance data from this pilot line will be used to qualify equipment purchases for high-volume production equipment. To many, it is clear that to participate in future 450mm production, equipment suppliers must participate in the pilot line.
However, not all vendors are being asked to participate, and for those that do, the terms for participation in the pilot line are daunting. How the industry will pay for and recover the massive R&D cost has not been resolved. Suppliers must weigh a decision to participate in pilot line development in conjunction with the possibility of not being qualified for production equipment orders from the world’s top chip manufacturers. The timing and quantity of these of these potential future orders are also not known.
These are difficult and complicated negotiations and decisions for the industry’s leading OEMs. They are even more complicated and difficult for the remainder of the supply chain.
While our leading equipment suppliers must sell products and services to chip manufacturers, many of the component and subsystem suppliers do not; they often serve multiple industries.
As the current collaboration model unfolds for 450mm development, its impact on a variety of technology suppliers — many of them exhibitors at SEMICON West — is uncertain. Approximately 90% of ASML’s components and subsystems are provided by outside suppliers. Another example, Applied Materials is dependent on 800 suppliers worldwide, with 75 prime strategic suppliers representing 80 percent of their annual procurement allocation.
On the transition of the industry to 450mm wafers — it is certain that the impact on the supply chain will be disruptive and significant. While it appears that G450C may be the primary path of coordination for the scale-up of wafer process tools, it is the OEMs that will be coordinating a complex multi-layered supply chain of component and sub-assembly providers. At SEMICON West for the first time, the major process tool makers communicated requirements and expectations to the larger group of supply chain participants that may not have direct access to the consortia pilot line.
SEMICON West 2012
At SEMICON West, the most knowledgeable and authoritative voices in the industry discussed these tough issues. Our objective is advance the dialog — to convey useful information to our attendees — and to serve as a platform for productive collaboration on these and other industry issues. All of the events at SEMICON West (keynotes, partner events, TechXPOTs, and technical presentations) allow key industry stakeholders to discuss where it makes sense to collaborate — and where it’s best to compete.
Please let me know if you have comments or questions at email@example.com.