NIST tips “hybrid” metrology method to test chips September 13, 2012 – Step aside, scatterometry and AFMs — there’s a new hybrid technique that’s both more precise and less expensive to measure features on a chip. The National Institute of Standards and Technology (NIST) says it’s combined scanning techniques and statistical data "using a Bayesian approach." They created a library of simulated data based on typical chip feature dimensions, to be compared with actual measurements made with AFM, scatterometry and other means. Comparing that analysis with actual measurements to extract valid measurement values can be costly — until one applies a little Bayesian statistical analysis. "In essence, if you’ve got a really small uncertainty in your AFM measurement but a big one in your optical measurements, the final uncertainty will end up even smaller than either of them," explains NIST scientist Richard Silver. Adding a few other measured values to the library model reduced uncertainty in some of the measurements — by up to a factor of three in some cases, NIST claims. This approach, the scientists say, will be a key part of measuring complex 3D transistor structures that are quickly approaching the 16nm node and beyond. In fact, Silver reveals that "IBM and GlobalFoundries have already begun developing the technique since we first described it at a 2009 conference, and they are improving their measurements using this hybrid approach." The research is described in the Sept. 1 issue of the journal Applied Optics. A silicon pillar, measuring <100nm along any of its sides, is the type of semiconductor feature in the crosshairs of a new NIST hybrid metrology technique to reduce measurement uncertainties. (Credit: NIST) Visit the Semiconductors Channel of Solid State Technology, and sign up for our WaferNEWS e-newsletter!