TSMC integrates Ge on Si in p-type FinFETs

Researchers are investigating the use of high electron-mobility materials as a way to improve FinFET performance, such as germanium (Ge) for the channels in p-type transistors. But it is difficult to grow Ge directly on a silicon substrate and usually many interface layers are built, each successive layer having a greater concentration of germanium. However, this gives rise to unwanted complexity and cost.

At this year’s International Electron Devices Meeting (IEDM), foundry TSMC will describe an alternative: a heterogeneous epitaxial growth process which for the first time enables Ge to be directly grown on Si. With careful process optimization, the researchers determined that when a fin’s height-width aspect ratio is ~1.4 or greater, imperfections at the Ge-Si interface (called threading dislocations) will be confined to the bottom part of the fin, leaving its top portion—the active area—defect-free. They demonstrated the technique by building devices with excellent subthreshold characteristics (slope=74mV/dec), good short-channel-effects control and high performance (1.2mA/µm at Vdd=1V). The work paves the way for the use of Ge in future p-type FinFETs.

The schematics show representations of the threading dislocations in (a) wide and (b) narrow active areas. In (b) the threading dislocations terminate at the sidewalls, leaving the top part defect-free.

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