IEDM 2012: Late papers on silicon photonics, large TFTs, III-V devices

December 11, 2012 – Our slideshow of 14 interesting papers at this week’s IEEE International Electron Devices Meeting (IEDM 2012), did not include what are often some of the more intriguing papers — the ones that come in late and are unavailable for preview. This year there are four such papers, and we’re now able to give you a sneak peek at them, being unveiled starting this afternoon and through the week at IEDM in San Francisco.

ZnNO for next-gen displays

Stability degradation, especially at high mobility regime, limits the application of oxide semiconductors in next-generation displays. Zinc oxynitride, with its high mobility characteristics and small bandgap, is getting attention as an alternative for pixel-switching devices in ultra-high definition and large-area displays. Researchers from Samsung Advanced Institute of Technology and Seoul National University will describe ZnON-thin film transistors (TFTs) with field effect mobility near 100 cm2/Vs and operation stability(< 3 V) under light-illumination bias-stress. The uniformity is observed to be suitable for display applications, and with mobility performance comparable to that of polysilicon (poly-Si). (#5.6, "High mobility zinc oxynitride-TFT with operation stability under light-illuminated bias-stress conditions for large area and high resolution display applications")

Structure of ES-type ZnON-TFT fabricated by photolithography. (left) Top view from optical microscope and (b) cross-sectional TEM image at the vicinity of contact region.

SnO transistor for BEOL-CMOS I/Os

Renesas Electronics’ LSI Research Laboratory has devised a new P-type amorphous SnO thin-film transistor with high Ion/Ioff ratio (>104) as a component to complement N-type IGZO transistors for on-chip voltage-bridging BEOL-CMOS I/Os on conventional Si-LSI Cu-interconnects. (The transistor gives standard LSIs a special add-on function to control high-voltage signals directly.) Their BEOL-transistor (BEOL-Tr) uses a wide-band-gap InGaZnO (IGZO) as the channel and cap-SiN/Cu-interconnect as the gate dielectric/bottom-gate electrode. Normally-off transistor characteristics with relatively high mobility, high-Vd tolerance, high Ion/Ioff ratio, have made the BEOL-Tr attractive for voltage-bridging devices mountable onto advanced MCUs and SoCs. Realization of P-type transistors to complement IGZO-based NFETs and form BEOL-CMOS is also a key function for more sophisticated applications, they claim. (#18.8, "High On/Off-ratio P-type Oxide-based Transistors Integrated onto Cu-interconnects for On-chip High/Low Voltage-bridging BEOL-CMOS I/Os")

XTEM of the integrated device structure with G/D offset of 0.5μm. SnO is integrated onto Cu interconnect to realize P-type BEOL-Tr with high Ion/Ioff ratio. Device integration requires only one mask addition.

III-V TFETs for the 7nm node

III-V tunneling field-effect transistors (TFET) for low-voltage logic applications have gained attention, but their nonoptimized carrier tunneling limit drive currents. Researchers from the Rochester Institute of Technology and SEMATECH set out to map III-V Esaki tunnel diode performance, engineering tunnel diodes (TD) with ultrahigh-current densities while maintaining large peak-valley current ratios. In this paper, they report a comprehensive experimental benchmarking of an Esaki diode, including GaAs, In0.53Ga0.47As, InAs, InAs0.9Sb0.1/Al0.4Ga0.6Sb, and InAs/GaSb. Engineering the hetero-junctions enhances peak and Zener current densities beyond homo-junctions, to a record 2.2 MA/cm2 and 1.1 MA/cm2 (-0.3 V), laying the groundwork for III-V TFETs at the 7nm technology node. (#27.7, "Benchmarking and Improving III-V Esaki Diode Performance With a Record 2.2 MA cm2 Current Density to Enhance TFET Drive Current")

(a) Cross-section of a TD fabrication process flow. (b) SEM image of a characteristic submicron TD after mesa etch. (c) schematic of a fully-fabricated TD.

Integrated CMOS silicon photonics on 90nm

IBM researchers in the US and Europe are demonstrating the first sub-100nm technology (a current 90nm base SOI logic technology) that allows monolithic integration of optical modulators and germanium photodetectors — putting optical and electrical circuits side-by-side on the same chip. The resulting 90nm CMOS-integrated nano-photonics technology is optimized for analog functionality to yield power-efficient, single-die multichannel wavelength-mulitplexed 25Gbps transceivers. (IBM has a fuller description of the technology in a separate press release.) (#33.8, "A 90nm CMOS Integrated Nano-Photonics Technology for 25Gbps WDM Optical Communications Applications")

Cross-sectional SEM view of a 90nm CINP metal stack with Ge PD embedded into the front-end. Zoomed-in image of a photodetector is shown on top left. Optical microscope top-down image is shown on the low left.

Angled view of a portion of an IBM chip showing blue optical waveguides transmitting high-speed optical signals and yellow copper wires carrying high-speed electrical signals.


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