IEDM 2012 slideshow 01

Intel’s 22nm trigates for SoCs

Multiple-gate transistors provide superior on/off control, enabling high drive currents to be achieved at a lower supply voltage than otherwise. At the International Electron Devices Meeting (IEDM), Intel will discuss its use of the multiple-gate approach to build a complete and versatile 22nm 3D tri-gate transistor technology platform for a range of system-on-chip (SoC) applications. The high-speed logic transistors have subthreshold leakages ranging from 100-nA/μm, while the low-power versions feature leakage of <50 pA/μm yet have drive currents 50% higher than 32nm planar devices. The process also yields high-voltage transistors (1.8V or 3.3V) with the highest reported I/O device drive currents for an SoC technology (NMOS/PMOS=0.92/0.8 mA/μm at 1.8V). The trigate technology platform features eight to 11 layers of low-k and ultralow-k carbon-doped oxide (CDO) interconnect at tight pitches for different applications. (#3.1, "A 22nm SoC Platform Technology Featuring 3-D Tri-Gate and high-k/Metal Gate, Optimized for Ultra-Low-Power, High-Performance and High-Density SoC Applications")

 

MIMCAP developed for 22nm trigate process.

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