IEDM 2012 slideshow 05

Hybrid floating gate nonvolatile memory

imec will describe — for the first time — a demonstration of ultra-thin hybrid floating gate (HFG) planar NVM cell performance and reliability. Results not only confirm the high potential of the HFG thickness scaling down to 4nm with improved performance, but also show excellent post cycling data retention and P/E cycling endurance. The optimized ultra-thin HFG planar cells show potential for manufacture and scalability for high density memory application. The stack consists of an ISSG tunnel oxide, a dual layer FG (PVD polysilicon + PVD TiN), a high-k IPD (ALD Al2O3) and an n-type polysilicon CG. (#2.2: "Ultra Thin Hybrid Floating Gate and high-k Dielectric as IGD Enabler of Highly Scaled Planar NAND Flash Technology")

 

XTEM of a Ge-channel FET with SiGe source/drain.

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