IEDM 2012 slideshow 14

Stacking NVM, CMOS

Researchers from the National Chiao Tung University’s National Nano Device Laboratories describe their work which looks toward future 3D layered CMOS for giant high-speed data-storage applications. They demonstrate for the first time a sequentially processed 3D hybrid chip by stacking low-temperature (LT) ferroelectric-like (FE-like) metal-oxide nonvolatile memory (NVM) and multilayered TFT inverters. The sequential layered integration achieved sharp transfer characteristics and stackable 3D FE-like NVMs with 100ns program speed thanks to low-thermal-budget (sub-400°C) plasma/laser processes and self-assembled FE-like metal-ion-mediated APS dielectrics, which resemble low-k dielectrics and metallization in multi-layered back-end interconnects, they explain. (#33.6: "3D Ferroelectric-Like NVM/CMOS Hybrid Chip by Sub-400oC Sequential Layered Integration")

 

TEM of sequentially processed 3D hybrid chip from gate and channel view.

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