CMOS is running out of steam, but what comes next? At the International Electron Devices Meeting in San Francisco, An Chen of GLOBALFOUNDRIES presented a survey of emerging nanoelectronic devices, which he divided into two categories: Charge-based and non-charge based.
Chen is well qualified to speak on the topic. In 2009, Chen was an assignee to the National Research Initiative (NRI) program of the SRC to work on emerging logic devices, including graphene electronics and spintronics. He is co-chair of the emerging research device group of the International Technology Roadmap for Semiconductors (ITRS). He is also an expert on memory technology, responsible for collaboration on emerging memories with industry consortia such as imec and SEMATECH.
“We can do better using better materials or device structures with better electrostatics (with existing CMOS technology),” Chen said, “but, facing fundamental limits, we have to ask ourselves ‘What are the solutions that may be available beyond CMOS?’”
One of the major challenges for scaling is escalating power density. “If we continue this trend, we’re going to some ridiculous number (see chart). That could limit how small we can shrink the device. That’s the real limit for the scaling,” Chen said. “We cannot really eliminate power leakage and we cannot reduce the supply voltage in proportion to device dimensions. We have to look for devices that may consume less power during switching,” he added.
To this end, low power beyond-CMOS devices have been developed based on novel state variables and/or computation mechanisms. Chen said that charge-based emerging devices may enable low-power computation by making the FET transition steeper or introducing new switching concepts. Another class of devices based on spin are another option; spintronics are one of the main types of noncharge emerging devices.
Chen provided an overview of the leading nanoelectronic devices, noting key features and potential challenges.
Tunneling FET (TFET)
The tunneling FET employs quantum mechanical band-to-band tunneling mechanism, and offers low Vdd, low power and an FET structure that is compatible with CMOS technology and infrastructure.
Challenges include: low saturation current, a lack of ability to extend low SS (subthreshold slope) over a wide current range; difficult engineering of the source tunneling region with regard to junction abruptness, bandgap, carrier effective mass, etc.; challenges with enhancing gate control on the internal E-field; and problems with interface states.
Impact Ionization MOS (IMOS)
IMOS devices employ a gated p-i-n structure operated in the reverse bias regime, where control of the gate impact ionization enables a steep increase of current via carrier multiplication. Key features include a steep sub-threshold slope and CMOS compatibility.
Challenges: IMOS devices are intrinsically slow due to the statistical avalanche charge multiplication process, and speed limitations due to carrier multiplication delay and statistical retardation delay. There are also limitations in scaling the intrinsic supply voltage, and susceptibility to hot carrier degradation.
Nano-electro-mechanical Switch (NEMS)
Advantages of NEMS, which operate as a mechnical switch with a cantilever beam as shown, include zero leakage and zero sub-threshold swing (in principle), high temperature tolerance, immunity to electromagnetic shocks, and compatibility with CMOS.
Challenges with NEMS include: Slow switching speed related to the beam movement and oscillatory pullout time; anoscale contact reliability; surface forces that causing sticking; tunneling-limited scaling; high pull-in voltage, and variability control.
Key features of the negative common gate FET: steep SS based on collective effects and internal feedback mechanisms; low-power solutions are possible; it’s compatible with CMOS; there have been demonstrations of negative capacitance in ferroelectric dielectrics and <60mV/dec SS in neg-Cg FET.
Challenges: the industry needs to identify appropriate materials (oxides and ferroelectrics) for the best swing with minimal hysteresis, integration of high quality single crystalline ferroelectric oxides on silicon; scalability has yet to be proven; speed is in question.
Resonant Tunneling Diodes (RTD)
Key features: Inherently high speed; negative differential resistance (NDR); integrating a pair of RTD with CMOS gate achieves bi-stable logic operation; precise control of layer thickness is important for fabrication.
Chen provided several examples of RTD device applications: Monostable-bistable transition logic elements, tunneling-based SRAMs and RTD-based spin-filters.
Single Electron Transistor (SET)
Key features: High speed; potentially high device density; potentially high power efficiency; novel functionalities and applications; compatibility with CMOS
Challenges include: size-temperature tradeoff; modest to low gain; large threshold voltage variation; parasitic capacitance; low output current and high output impedance; limited fan-out; low noise immunity; immature fabrication process.
Key features: FET-type structure with CMOS compatibility; fast phase transition speed; good scalability.
Chen said there has been limited progress on FET recently, although two-terminal Mott devices have been explored for memory applications. Other challenges include: transition temperature; a lack of fundamental understanding of the gate oxide (functional channel interface and the local band structure changes under E-field is limited); Mott transition often coupled with thermal effects and structural changes.
Quantum Cellular Automata (QCA)
QCA, which has been experimentally demonstrated with semiconductor, molecular and magnetic dots could provide potentially low-power, novel information processing and transfer mechanisms, and majority gate operation.
Challenges include operating temperature and patterning at extreme scales.
The atomic switch is based on the formation/annihilation of a metallic atomic bridge between two electrodes, which can be gate-controlled.
Key features: Highly scalable; low operation voltage and power; two-terminal device for memory is the same as the conductive-bridge RAM (CBRAM); it’s a relatively simple process with potentially low cost, and is 3D stackable.
Challenges: Improve performance of 3-terminal devices (speed, endurance, uniformity); stability and variability may be concerns; speed is determined by ionic transport and electrochemical reactions at the reactive electrode interface; and a better understanding of the operation mechanisms is needed.
Key features: Spin degree of freedom enables additional signal modulation and control; FET-type structure and compatibility with CMOS; dissipation-less transport in theory; and nonvolatility and programmability.
Challenges: Magnetic materials and processing; requires high efficiency of spin injection and detection for sufficient on/off ratio; strength of gate modulation of spin-orbit interaction; and spin relaxation and lifetime.
Other Spin Transistor concepts include spin-MOSFETs, nonmagnetic spin transistors, non-ballistic spinFETs, and magnetic bipolar transistors.
Nanomagnet Logic (NML)
With NML, logic bits are encoded in magnet polarization directions and computation is by magnetic coupling. Key features: Majority logic operation; room-temperature operation; potentially low switching energy; nonvolatility; potentially zero standby power; and regularity in layout and design, which makes novel architectures more feasible.
Challenges: Clocking field design and optimization; defect tolerance (e.g., misalignment); slow switching speed; scalability in question; layout efficiency; wire crossing.
Chen noted that room-temperature majority logic gate and cascaded logic operation based on NML have been demonstrated, and that a transition from in-plane to perpendicular magnetization may further improve NML operations.
Spin-Transfer-Torque (STT) for Logic
STT for logic, which is enabled by a magnetic tunnel junction (MTJ), can be a majority logic gate based on phase locking of STT oscillators, or it can be based on STT switching in a multi-terminal magnetic tunnel junction (e.g., separate writing and sensing paths of MTJ and third-terminal controls).
Key features: Leverages technologies from STT-RAM; potentially low power; multiple logic states possible; non-volatility and programmability; STT oscillator may provide clock functions; and it may enable novel architectures and designs based on combined logic and memory functions.
Challenges: Material and integration; reducing switching current and power; and impedance mismatch with CMOS.
Chen said many conceptual device proposals are supported by device and circuit models and there have been an increasing number of experimental demonstrations, plus significant effort on architectural design.
Spin Wave Logic
With spin wave logic, logic information is encoded in spin wave phase or amplitude and computation is by wave interference. Key features: Parallel data processing on multiple frequencies on the same device; potentially low-power operation; integration with magneto-electric cells enables nonvolatile information storage; majority logic gate operation; and information transmission without charge transfer and potential interconnect solution for spintronic devices.
Challenges: Efficiency and power consumption of spin wave generation; spin wave signal degradation during propagation along spin waveguide; low group velocity and speed of signal propagation (~ 107 cm/s); device scalability limited by spin wave length; and there’s the potential for inductive cross-talk.
Chen said prototype spin wave logic devices have been demonstrated, including wave generation, propagation, and detection.
Domain Wall Logic
Information is stored in a movable domain wall in ferromagnetic wires. It’s an all metallic logic, with potentially low power. Challenges include a high current to drive domain wall migration, a relatively slow switching speed, and the need for an external clock.
All Spin Logic
Key features: Magnets inject spin + spins switch magnets; uses both analog (spin current) and digital (bistable magnet) properties; potentially very low power; low voltage clocking operation; and suitable for non-Von Neumann architectures.
Challenges: Room-temperature switching in a multimagnet networks interacting via spin currents; Introduction of high anisotropy magnetic materials into demonstration; proper choice of channel materials; and current density. So far it’s only theory without direct experimental demonstrations
Bi-layer pseudo-Spin FET (BiSFET)
BiSFETs are based on exciton condensation in bi-layer graphene. It potentially offers low power and fast speed, but challenges exist in terms of operating temperature, device fabrication (e.g., graphene and dielectric quality, alignment, thickness control, etc.), and a low noise margin.