Lifting the veil on silicon interposer pricing

At the recent Georgia Tech-hosted International Interposer Conference, Matt Nowak of Qualcomm and Nagesh Vordharalli of Altera both pointed to the necessity for interposer costs to reach 1$ per 100mm2 for them to see wide acceptance in the high-volume mobile arena. For Nowak, the standard interposer would be something like ~200mm2 and cost $2. The question that was posed but unanswered was: "Who will make such a $2 interposer?"

Less than a month later, this question began to be answered as several speakers at the year-ending RTI ASIP conference (Architectures for Semiconductor Integration and Packaging) began to lift the veil on silicon interposer pricing.

Sesh Ramaswami, managing director at Applied Materials, showed a cost analysis which resulted in 300mm interposer wafer costs of $500-$650 / wafer. His cost analysis showed the major cost contributors are damascene processing (22%), front pad and backside bumping (20%), and TSV creation (14%).

Ramaswami noted that the dual damascene costs have been optimized for front-end processing, so there is little chance of cost reduction there; whereas cost of backside bump could be lowered by replacing polymer dielectric with oxide, and the cost of TSV formation can be addressed by increasing etch rate, ECD (plating) rate, and increasing PVD step coverage.

Since one can produce ~286 200mm2 die on a 300mm wafer, at $575 (his midpoint cost) per wafer, this results in a $2 200mm2 silicon interposer.

Lionel Cadix, packaging analyst of Yole D

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