STMicro: 28nm FD-SOI is ready for manufacturing

December 12, 2012 - STMicroelectronics is getting out of the JV chip business with Ericsson, but it’s still full-steam ahead for its use of fully-depleted silicon-on-insulator (FD-SOI) technology with its partners.

The "feature-complete and silicon-verified" 28nm planar FD-SOI Technology Platform, now open for preproduction from the Crolles 300mm manufacturing facility, encompasses a full set of foundation libraries (std-cells, memory generators, I/Os, AMS IPs, and high speed interfaces), and a design flow ideally suited for developing high-speed and energy-efficient devices. Measurements on a multi-core subsystem in an ST-Ericsson NovaThor ModAp platform revealed a maximum frequency exceeding 2.5Ghz and delivering 800 MHz at 0.6V, according to Jean-Marc Chery, EVP/GM, digital sector, and CTO/chief manufacturing officer of STMicroelectronics.

"Post-processing wafer testing has allowed us to prove the significant performance and power advantages of FD-SOI over conventional technologies, building a cost-effective industrial solution that is available from the 28nm node," he stated. ST-Ericsson will use the FD-SOI technology in its future mobile platforms demanding high performance yet low power consumption.

Porting libraries and physical IPs from 28nm bulk CMOS to 28nm FD-SOI is "straightforward," and the process of designing digital SoCs with conventional CAD tools and methods in FD-SOI is identical to bulk, due to the absence of MOS-history-effect, ST says. FD-SOI enables production of highly energy-efficient devices (dynamic body-bias allows instant switch between high-performance mode and a very-low-leakage state), transparently for the application software, operating system, and the cache systems. FD-SOI also can operate at significant performance at low voltage with superior energy efficiency versus bulk CMOS.

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4 thoughts on “STMicro: 28nm FD-SOI is ready for manufacturing

  1. Sang Kim

    First, 28/32nm planer bulk silicon technology is in volume manufacturing for over couple of years by Intel, TSMC, Samsung and others today. Intel is in high volume manufacturing of 22nm trig-ate FinFETs for almost a year. Therefore, STMicro’s 28nm FD-SOI seems too late, but STMicro claims its devices have higher speed and more energy efficient compared to its rivals. IBM developed FD-SOI technology for the first time, but was not successful in manufacturing up to now because of the following four main reasons: Floating body effect, self-heating, ultra-thin SOI approximately 7nm required for 28nm node, and high SOI wafer costs. In June 2012 SOI Conference Soitec announced high volume manufacturing of 28nm SOI wafers with 12nm SOI thickness, but not 7nm. That is, Soitec can’t deliver 7nm SOI that is required to suppress transistor leakage current or short channel effect. For 22nm FD-SOI 6nm or less SOI thickness will be required. STMicro doesn’t mention how it has resolved the four problems described above. SKim

    Reply
  2. Giorgio Cesana

    Thank you for those comprehensive questions. Responding gives us a chance to provide details of the advances of UTBB FD-SOI technology and remove any doubts you may still have about it.

    1. Ultra-Thin Body and Buried Oxide (UTBB) FD-SOI technology is very different from Partially-Depleted technologies manufactured before. Those partially-depleted technologies were affected by floating-body effects where the body was subject to an uncontrolled charging/discharging that led transistor behavior to depend on the previous transitions –i.e. making them suffer from a kind of memory effect.
    In UTBB FD-SOI technology, hybridation lets us contact the body, so it is not left floating, overcoming the problems with PD-SOI technologies.

    2. Self-heating is also a problem that exists with Partially-Depleted SOI technologies, where the Buried Oxide thickness (~150nm) was thermally isolating transistors from the substrate, leading to self-heating effects.
    UTBB FD-SOI technology offers two advantages to overcome this self-heating:
    - The Buried Oxide (BOX) is extremely thin (only 25nm thick in 28nm technology), offering significantly less thermal resistance;
    - The big diodes, the drift mos, the vertical bipolar, some resistors… are all implemented on the “hybrid” bulk part, eliminating even the thin BOX below them.

    3. Wafer thickness: The ST process specification is for wafers with 12nm thick silicon (+/- 5A). Process manufacturing then “uses” part of the silicon film for the manufacturing of the transistors, leading to a final 7nm film below the transistors.

    4. Wafer costs: UTBB FD-SOI technology manufacturing uses up to 15% fewer steps vs. our bulk planar 28LP HKMG gate-first technology. This process simplification, by itself, is capable of totally compensating for the current substrate cost difference. Then, we expect in high volume production, UTBB FD-SOI die costs should be even better than bulk planar, with substrate-cost erosion and with UTBB FD-SOI improving electrical yield over bulk planar.

    We hope these answers convince you, as they’ve convinced us, of the suitability of FD-SOI technology for sub30nm semiconductor manufacturing.

    Reply
  3. Sang Kim

    First, STM’s UTBB FDSOI has manufacturability issues: the UTBB consists of an extremely thin 7nm or 0.7A (Angstrom) that is less than 1A channel layer confined by the 25 nm buried oxide for 28nm technology node. Please describe precisely how the wafers with the initial 120A channel thickness were reduced to 0.7A in volume manufacturing. The STM wafer process spec: +/- 5A equivalent to +/- 50nm is more than 4 times thicker than the initial wafer thickness (12nm)! One of the problems with UTBB is that the channel is so thin (0.7A) that the transistor on-current, I-on is relatively small. The attempt to increase the I-on by the substrate bias through the 25nm buried oxide has shown not much improvement because the substrate bias affects both source and drain voltages and gate capacitance. IBM’s new roadmap for FDSOI scaled down to 10nm doesn’t include the UTBB.
    Second, in my opinion the PD (partially depleted) SOI technology was one of the most successful products manufactured by IBM extended to several technology nodes. In fact, PDSOI showed some features that the planer bulk technologies didn’t have such as latch-up elimination and increased immunity to cosmic ray induced logic errors. The major differences between PDSOI and FDSOI are that PDSOI has a significantly deep floating body and long gate length, Lg compared with FDSOI. As a result, PDSOI behaves like a planer long channel bulk transistor, causing minimum self-heating. That is why the PDSOI products were successfully manufactured by IBM, but not FDSOI. IBM has not demonstrated the manufacturability of FDSOI on any technology node. FDSOI after exit from PDSOI as the channel length shrinks showed the following two phenomena: turn-on of the hot carrier induced parasitic bipolar transistor and high transistor leakage current. In order prevent the phenomena IBM adopted an ultrathin 7nm channel thickness for 28nm FDSOI, the same thickness as SMT’s UTBB, but no buried oxide. IBM will have the same manufacturability issues and self-heating as well.
    Giorgio responses do not convince me because STE has not published its transistor data such as transistor electrical transfer characteristics: the basic measurements dId/dVg and dId/dVd so that we can compare with those already published by Intel, TSMC, Samsung and others for planer bulk 28nm node. If STM’s UTBB FDSOI is production ready, such basic transistor measurements will be readily available. SKim

    Reply
  4. Giorgio Cesana

    Thank you Mr. Kim for your comments. Here are a few further responses about UTBB FD-SOI manufacturability in general and ST’s process, in particular.

    - Thin silicon thickness: Perhaps I have not been clear with my previous reply. We are moving from a raw 12nm thick silicon film (=120A, +/- 5A) to a final film of 7nm (=70A) under the transistors. This is a perfectly repeatable process and is already qualified for production at ST.

    - Effectiveness of body biasing through the back side: Thanks to the thin BOX, among the many papers published, you may read O. Faynot et al, “Planar Fully Depleted SOI Technology: a powerful architecture for the 20nm node and beyond”, International Electron Device Meeting Technical Digest, 2010

    - Advantages of UTBB FD-SOI: You should read A. Khakifirooz at al., “Extremely thin SOI for system-on-chip applications”, CICC 2012. This paper, written by authors from IBM, STMicroelectronics, LETI, Renesas, and GLOBALFOUNDRIES, should convince you of the advantages.

    - 28nm FD-SOI technology details: This information has recently been published at IEDM 2012 (F. Arnaud et al., “Switching Energy Efficiency Optimization for Advanced CPU Thanks to UTBB Technology”).

    Most important, to prove manufacturability, the recent announcement from ST-Ericsson about their NovaThor L8580 product, which was demonstrated at CES, is capable of running its eQuad ARM cores up to 2.8GHz, while still fitting a mobile smartphone thermal footprint and proving (if needed) the potential and the maturity of FD-SOI technology.

    Unfortunately, we can not provide further details about the 28nm FD-SOI technology other than what has been detailed in the latest announcements as well as the many papers that we have published on the subject. Further details are, of course, available to our customers, though they cannot be publicly disclosed.

    Best regards

    Giorgio Cesana, STMicroelectronics

    Reply

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