2013: An economic outlook for the global IC market

By Mark Thirsk, Managing Partner, Linx Consulting LLC.

Past contributors have often noted a correlation between the semiconductor market growth and global GDP.  With careful correction this correlation can be used to forecast future IC market trends, although the process is not straightforward.

The consensus forecast for global GDP 2013 is now below trend at 2.6%, only a slight improvement over 2012, and less than the 3.2% seen in 2011.  The US approach to solving fiscal Cliff is an excellent example of the difficulty governments are having in developing strategies to address unprecedented economic problems, although political solutions, however imperfect, helps to stabilize expectations, and solidify financial markets.  In Europe, mild recession will continue through most of 2013, and Asia (excepting Japan) will likely show the best overall growth rates in the coming 12 months as measures to cool the Chinese economy are relaxed.

These extraordinary conditions in the global economy lead to wide variations in economic forecasts with an upside as high as 3.5 % growth, and a pessimistic case as low as 1%.  Against this backdrop, meaningful macroeconomic demand-side forecasts are difficult to develop.

Linx has worked with Hilltop Consulting to implement a proven macroeconomic forecasting tool that takes into account the global economic shocks and volatility to develop an Silicon area forecast for the global semiconductor industry.  Predictions for 2013 show several notable trends: 

  1. Overall Si area growth for 2013 should average approximately 6%. 
  2. The first quarter and the second half are likely to show slower growth than the second quarter.  This trend is part of a seasonality which has been swamped by economic volatility over the last 3 to 4 years. 
  3. The modest growth forecast for 2013 is predominantly demand driven since inventory levels have not shown a significant spike in 2012.

The overall picture of Si area growth breaks down into the expected performance of device segments and technology nodes.  Despite the shift to consumer electronics and mobile platforms we expect growth to be concentrated in CMOS products at ≤ 65nm with a continuing slowing of unit growth and analog and discrete devices.  Strongest growth will remain with flash memories, and advanced foundry logic devices targeted at tablets and phones.

In contrast to advanced memory and logic processing, approximately 56% of the Si production continues at design dimensions in excess of 90 nm on wafer sizes of 200 mm or smaller.  This market segment is extremely sensitive to economic volatility and has declined somewhat in the last four years.  Manufacturers of these devices are often capital constrained and extremely cost sensitive, leading to little process innovation and limited capacity expansion.

On a technology basis, despite tight capital budgets, the introduction of devices at 28 and 22 nm half pitches continues apace, and significant process challenges are driving increased complexity and resultant challenges in patterning, cleaning, and deposition throughout the device manufacturing process.  2012 is forecast to have produced more silicon area at 32 nm than any other node, and the introduction of low 20 nm half pitches and flash has continued to grow startling rates.  Significant challenges also exist in the in the advanced device markets due to geometric constraints and physical limits in scaling planar devices.  At a time when lithography is unable to scale continuing device shrinks results in added complexity in critical patterning steps and demands the addition of multiple lithography steps to achieve a single pattern level.

Manufacturers of logic and memory alike are working to develop substitute technologies for planar transistors, MIM capacitors and floating gate structures.  The broad introduction of metal gate finFETs, new types of storage cells, and three-dimensional memory stacks is still several years away, and this is driving interest in the adoption of three-dimensional packaging technologies such as through silicon vias to continue delivering increasing functionality in a package.

Despite the headwinds of increasing layer counts to compensate for the lack of high resolution lithography, and the need for new deposition technologies needed for novel processes and device architectures, we expect a small group of wafer makers to continue to chase these advanced technologies, while also pushing to implement 450 mm wafers.  Few of these technologies will see implementation in 2013, but they will be the focus of headlines as new breakthroughs are made, while the semiconductor industry continues its trend of remarkable success.

 

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