By Richard Gottscho, Ph.D., EVP – Global Products, Lam Research Corporation
The semiconductor industry is evolving and facing unprecedented technology and economic hurdles. Limits imposed by planar technology and a stalled lithography roadmap threaten to slow down the rate at which density, cost, and speed improvements can be made. As this industry has shown before, however, there is more than one way to skin a cat. FinFET devices offer superior speed at lower power consumption. 3D NAND enables bit scaling of flash memory without the need of lithography roadmap extension. Multiple patterning extends the lithography roadmap. Through-silicon via (TSV) technology brings increased density, lower power consumption, and faster computing to mobile applications. But, these inflection technologies have their own set of challenges.
FinFETs are challenging to etch because the 3D topography requires long over-etching to clear corners; etching selectivity becomes of paramount importance. Atomic-scale precision is required across not only the wafer, but also from wafer-to-wafer and from fab-to-fab. Etch costs increase for all these reasons. FinFET metal gates have high-aspect-ratio features that must be filled without voids with thin, conformal, low-resistivity diffusion barriers using atomic-layer deposition.
3D NAND is formed by first depositing alternating layers of insulators and conductors, then etching through those layers to create a 3D array of interconnected transistors. The layers are best etched non-selectively while maintaining high selectivity to the mask. Deposited films must be atomically uniform in smoothness and thickness. Long process times and atomic-scale precision in both deposition and etching drive cost.
Multi-patterning relies on etching and deposition extensively to fabricate high-density masks. To preserve the high-resolution, high-aspect-ratio pattern, films must be mechanically strong with 100 percent step coverage. Costly long process times and atomic-scale precision are yet again required.
One cost challenge in fabricating TSVs results from etching slowed by high-aspect ratios while needing to minimize sidewall roughness. After the via is etched, atomic-layer deposition of conformal and void-free liners and barriers is performed to enable bulk plating of copper interconnects. Cost is still inhibiting growth of the TSV market.
While solutions are available to extend Moore’s Law, these solutions come at considerable increases in cost and complexity. As it has in the past, this industry will find more innovative solutions to overcome the challenges of inflection.