By Dr. Howard Ko, Senior Vice President and General Manager, Silicon Engineering Group, Synopsys, Inc.
Nowadays, the mention of 3-D scaling in a semiconductor context conjures up images of the increasingly popular FinFET devices used in advanced logic processes or the stacking of multiple die in a 3D-IC. Yet there are a variety of developments in another type of 3-D scaling that are likely to have a similarly large impact on semiconductors in the near future – 3-D devices for NAND flash.
Whenever we communicate with our mobile phones, catch up on the latest news in our tablet computers, or snap those memorable holiday family photos with our digital cameras, we are relying on an indispensable semiconductor technology: the NAND flash memory. Over the past two decades, NAND flash memory has become one of the linchpins of the semiconductor market with revenues of approximately $21B in 2012 according to iSuppli. As in other semiconductor technologies, NAND flash evolution has been driven by density, performance and cost improvements. And as in planar CMOS logic, NAND flash technology has been progressively scaled to smaller feature sizes, becoming the process leader in driving the smallest line-widths in manufacturing as evidenced by the current 1x-nm (~19-nm) process node. Yet, despite plans to scale down to the 1y-nm (~15-nm) and possibly 1z-nm (~13-nm) nodes, the traditional planar floating gate NAND flash architecture is approaching the scaling limit, prompting the search for new device architectures. Not to be upstaged by the planar to 3-D (FinFET) transition in logic devices, NAND flash has embarked on its own 3-D scaling program, whereby the stacking of bit cells allows continuous cost-per-bit scaling while relaxing the lateral feature size scaling.
A number of 3-D NAND flash options have emerged: pipe-shaped bit cost scalable (P-BiCS); terabit cell array transistor (TCAT); vertical-stacked array transistor (VSAT); and vertical gate (VG) NAND. All of these share a common attribute: they are fabricated by depositing polysilicon on oxide to form a thin body for the cell channel, with a sidewall oxide-nitride-oxide stack serving as the charge-trapping storage element. 3-D NAND memories are complex structures with unique challenges such as the granular composition of the polysilicon channel, which introduces variability. To support 3-D NAND development, Sentaurus TCAD is used by industry leaders to analyze the impact of polysilicon grains and their boundaries on the electrical performance of the cell. The use of TCAD has provided important insights into the physics of operation of these memory cells and has been instrumental in optimizing the process and cell design to improve performance and reliability, thereby matching its role in the early exploration and optimization of the better known 3-D logic counterpart, the FinFET.