Challenges and innovations on front-end and 3D TSV

frederic-raynalFrederic Raynal, CTO, Alchimer

Looking at 2014, we see challenges and innovations in both the front-end semiconductor and 3D TSV markets.

In the front end, we are seeing a focus on further scaling to smaller nodes. For logic, TSMC has just announced it is ready for 16nm node, and Intel is ramping to 14nm. Industry experts question whether shrinking to 10nm will be feasible from a technology perspective. For example, at 10nm, most of the layers in copper interconnection must be between 2 and 4nm thick, which poses challenges for the technologies used in volume manufacturing. Controlling the thickness of single as well as dual damascene layers requires new technologies, such as electrografting, which is much more controllable and able to meet emerging requirements. We strongly believe that new technologies will need to be introduced for logic at the 10nm node and memory at the 16nm node, with ramp occurring at the 10nm node for the industry to maintain the path of Moore’s law.

We also expect to see 3D TSVs ramping to production in 2014. This is another area where innovation is needed that can meet demanding performance requirements while controlling costs, since cost is currently holding back widespread adoption of 3D-ICs. High-aspect-ratio (HAR) vias are a good candidate for new technology like electrografting, which is cost competitive compared with electrochemical deposition, chemical vapor deposition or physical vapor deposition, and delivers higher performance. For example, 40:1 aspect-ratio capabilities were recently demonstrated for electrografted barrier and seed layers, and 20:1 aspect ratio for fill processes.

It is widely expected that both the front-end and packaging areas of the semiconductor industry are poised for growth in 2014. Continued technology innovations will be a key driver in both areas in order to meet emerging performance requirements while successfully controlling cost and overcoming current roadblocks.

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