Experimental Demonstration of Monolithic 3D-IC Technology

Monolithic 3D-ICs

Monolithic 3D-ICs

Sizes of today’s TSVs are in the 5um range. Monolithic 3D technologies offer TSVs in the 50nm range, which allows dense connectivity between different layers in a 3D-IC. In this paper from CEA-LETI, such dense connectivity is shown to provide 55% area reduction and 47% energy-delay product improvement for a 14nm FPGA design. Transistor technologies that allow monolithic 3D integration are experimentally demonstrated.

[12.1. P. Batude, et al., “3D Sequential Integration Opportunities and Technology Optimization”, CEA-LETI (Invited)]

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