Through Silicon Vias (TSVs), an important component of 3D chip stacking technology, typically have a “keep-out zone” around them, where transistors are not placed. This is due to co-efficient of thermal expansion mismatch between the copper TSVs and silicon, which introduces tensile stresses in the silicon and changes transistor performance. These keep-out zones are typically >7mm, which adds constraints for design and leads to die size penalties.
In this work from GLOBALFOUNDRIES, a CMP stop layer is specially designed such that it introduces compressive stresses on the silicon and compensates for the tensile stresses introduced due to copper TSVs. The result is a near-zero keep-out zone for TSV technology, that is validated with simulations as well as experiments.
[5.2. M. Rabie, et al., “Novel Stress Free Keep Out Zone Process Development for Via Middle TSV in 20nm CMOS”, GLOBALFOUNDRIES]