Embedded DRAM is becoming important for high-performance ICs. This necessitates integrating sophisticated 3D capacitor structures into the interconnect stack. This paper from Intel shows a process integration flow for a 3D capacitor that provides excellent yield and retention times greater than 100us at 95oC. The 3D capacitor advances allow an industry-leading 17.5Mb/mm2 memory array density.
[8.1. R. Brain, et al., “Integration of a 3D Capacitor into a Logic Interconnect Stack for High Performance Embedded DRAM SoC Technology”, Intel (Invited)]