“Interconnect” is the wiring system that connects transistors and other components on an integrated circuit, or computer chip. It may also refer to chip-to-package or chip-to-chip interconnections. Transistor speed used to be the limiting factor for chip performance, but with today’s multi-million-transistor chips, the interconnect itself has become a limiting factor. This is because the electrical resistance of the wires, or lines, increases as they are made thinner to accommodate more transistors. It also arises because capacitive coupling can occur among adjacent lines spaced very closely together. Both inhibit the passage of signals.
The interconnect problem threatens to retard the development of chip technology, which in turn threatens the progress of the electronics industry, one of the world’s largest. IITC/AMC papers address this problem directly.
Copper lines offer less resistance and higher current-carrying capability than the previously used aluminum lines, but at small geometries surface scattering effects increase the effective resistivity, which has led to interest in alternative conductors such as graphene and carbon nanotubes. Standard silicon dioxide insulator (or dielectric) around the lines creates a high parasitic capacitance at narrow spacings with concomitant signal delays and increased power consumption. This had led to the introduction of and continued search for substitute materials. A dielectric’s relative permittivity is expressed as “k.” The lower the k, the faster the signal propagation speed and the lower the power consumption. (Vacuum, the perfect low permittivity material, has k=1; silicon dioxide has k~4.) The challenge with dielectric materials with very low k-values is that they are porous and generally more fragile than oxide dielectrics. Carbon-doped oxide (or SiCOH) low k dielectrics can be easily damaged by typical chip-making processes such as exposure to harsh plasma during photoresist-stripping and to chemical-mechanical polishing, used to planarize each interconnect layer.
The semiconductor industry introduced the first carbon-doped low k dielectrics with k~3 in the 90nm technology node. The 45/40nm nodes saw introduction of enhanced SiCOH low k (k~2.7) and early porous ultra low k (ULK, k~2.4). The 32/28nm nodes developed mechanically robust ULK films (k~2.5), which are becoming pervasive in the 22nm technology entering early production. Focus in the 20nm and 14nm nodes has been on patterning challenges but research and development on dielectrics with enhanced mechanical properties and extreme low k (k~2) remains active. Additionally, at the advanced technology nodes’ smaller dimensions, there is an increased focus on new materials and processes to improve the reliability and manufacturability of copper based interconnects. These include barrier, seed, copper filling, and capping technologies.